Series switches for power delivery. A regulator operated as a current source is arranged in parallel with a switched capacitor divider. A switched capacitor divider is configured in series with a plurality of linear regulators with each regulating one of a plurality of voltage outputs from the switched capacitor divider. In another embodiment, a series switch bridge has a first pair of switches connected in series with a second pair of switches across a voltage input, each switch within a pair of switches is switched in-phase with the other while the first pair of switches is switched out of phase with the second pair of switches. A balancing capacitor is coupled across one switch in both the first and second pair to be in parallel when either of the pair of switches is closed to reduce a charge imbalance between the switches.

Series and parallel hybrid switched capacitor networks for ic power delivery

A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage such that it significantly reduces a DAC settling time interval during each bit trial. In one exemplary embodiment, the switched-capacitor circuit having first and second groups of capacitor banks is coupled to a first input of a comparator and to a control circuit which provides control signals such that during a switching sequence, an equal value of capacitance is selected from each of the first and second groups of capacitor banks to reduce the DAC settling time interval, thereby improving the conversion rate.

Method and apparatus for segmented, switched analog/digital converter

An SAR ADC provides increased immunity to noise introduced by time varying noise components provided on reference potentials (VREF). Reference voltage noise contributions are canceled by introducing a reference voltage component to a pair of binary weighted capacitor arrays (NDAC and PDAC) during bit trials, which are presented to a differential comparator as a common mode signal and rejected. During sampling, select elements in either the PDAC or the NDAC also obtain a reference voltage contribution. Although the sampled VREFsi gnal may have a noise contribution, the noise is fixed at the time of bit trials, which can improve performance. Generally, the scheme provides a 50% reduction in noise errors over the prior art for the same VREFn oise. Additional embodiments described herein can reduce noise errors to 25% or even 12.5% over prior art systems.

Successive approximation register analog to digital converter with improved immunity to time varying noise

A 12-bit 31.1- $\mu \text{W}$ 1-MS/s successive approximation register analog-to-digital converter (ADC) with on-chip input-signal-independent calibration achieving 100.4-dB spurious-free dynamic range is presented. The proposed calibration overcomes the drawbacks of the conventional split-ADC calibration while maintaining fast convergence. The calibration only needs one ADC and is input signal independent. Three techniques are proposed to help achieve this, including shuffling of mismatched MSB capacitors, MSB–LSB swapping, and partial MSB unit-capacitor dithering. In addition, partial bit trial and split-bottom switching circuit techniques are proposed. Silicon results fully validated the design and show 16-bit linearity with only 256-fF sampling capacitance.

A 12-Bit 31.1- $\mu$ W 1-MS/s SAR ADC With On-Chip Input-Signal-Independent Calibration Achieving 100.4-dB SFDR Using 256-fF Sampling Capacitance

A device ( 200, FIG. 2 ) includes receive hardware ( 204 ) which performs analog-to-digital conversion. In accordance with an embodiment of the invention, the receive hardware includes a pipelined analog-to-digital converter ( 320, FIG. 3 ). Sample-and-hold circuitry ( 410, FIG. 4 ) associated with the analog-to-digital converter is configured (FIGS. 8 , and 12 - 14 ) and switched (FIG. 7 ) in a manner that provides intermediate frequency to baseband downconversion and skew-insensitive double-sampling.

Double-sampled, sample-and-hold circuit with downconversion

A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched-capacitor circuit comprises a plurality of capacitors arranged according to several embodiments.

Method and apparatus for split reference sampling

An amplifier system can include a feedback amplifier circuit having an amplifier, a feedback capacitor connected between an input terminal and an output terminal of the amplifier by at least one first switch, and a reset capacitor connected across the feedback capacitor by at least one second switch and between a pair of reference voltages by at least one third switch. During an input-signal processing phase of operation, a control circuit may close the at least one first switch and open the at least one second switch to electrically connect the feedback capacitor between the input and output terminals to engage feedback processing by the feedback amplifier circuit, and close the third switch to electrically connect the reset capacitor between the first and second voltages to charge the reset capacitor to a selectable voltage difference. During a reset phase of operation, the control circuit may open the at least one third switch, close the at least one second switch and open the at least one first switch to electrically connect the reset capacitor across the feedback capacitor to reset the feedback capacitor using the reset capacitor. The amplifier system can optionally include a plurality of the feedback amplifier circuits.

Reset and resettable circuits

A switched-capacitor circuit for use in analog-to-digital conversion samples an input signal with respect to a reference voltage, without having to generate the reference voltage, by using charge redistribution. The switched-capacitor circuit prevents the need to dissipate power while producing the reference voltage. The switched-capacitor circuit is coupled to a comparator and to a logic circuit which provides control signals for switching. The switched­capacitor circuit comprises a plurality of capacitors arranged according to several embodiments

Bruce Amazeen

Papers

Method and apparatus for split reference sampling

Reset and resettable circuits

Method and apparatus for voltage reference generation by charge redistribution for use in analog to digital conversion