Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, using various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

Monolithic integration of logic, control and high voltage interface circuitry

A bipolar transistor is provided with a collector layer of a first conductive type, a base layer of a second conductive type formed at a surface of the collector layer, and an emitter layer of the first conductive type formed at a surface of the base layer. An emitter electrode is connected to the emitter layer. Base electrodes are connected to the base layer and surround the emitter electrode. Emitter electrodes are connected to the collector layer and surround the base electrodes.

Bipolar transistor and semiconductor device having the same

A process is used to form in a common substrate (12) a PMOS transistor (200) of the lightly-doped drain (LDD) type, an NMOS transistor (100) of the LDD type and a vertical n-p-n bipolar transistor (300). In particular: the steps used to form an n-type well (214) for the PMOS transistor (200), and an n-type drain extension well (114) for the NMOS transistor (100), are also used to form the n-type collector (314) of the bipolar transistor (300); the steps used to form the p-type extension well (208) for the PMOS transistor (200) are also used to form the p-type base (308) of the bipolar transistor (300), the source/drain implantation step for the NMOS transistor (100) is also used to form the emitter (310) and a contact region (312) for the collector of the bipolar transistor (300); and the source/drain implantation step for the PMOS transistor (200) is used to form a contact region (311) for the base of the bipolar transistor (300).

Process for forming vertical bipolar transistors and high voltage CMOS in a single integrated circuit chip

Monolithic integration of digital logic circuitry, precision control circuitry, and high voltage interface circuits on the same semiconductor chip is achieved, including various combinations selected from D-MOS, vertical NPN, lateral NPN, PNP, P-MOS, N-MOS, and J-FET components. Cathode driver circuits for a plasma display panel are integrated with this technology. Other applications include automotive and television circuits.

Process for monolithic integration of logic, control, and high voltage interface circuitry

An improved bipolar transistor structure formed in a very small area of a thin epitaxial layer on a planar surface of a silicon substrate of first conductivity type, said very small area of the thin epitaxial layer having vertical sidewalls extending to the planar surface of said substrate, said area of thin epitaxial layers containing in the order recited a shallow depth emitter region of a second conductivity type having an exposed planar surface, a shallow depth base region of said first conductivity type, and a shallow depth active collector region of said second conductivity type, an elongated region of said first conductivity type surrounding said emitter, base and active collector regions, said elongated region being contained within and coextensive with said vertical sidewalls of said small area of said thin epitaxial layer, whereby the base collector capacitance is materially reduced due to the very small area of the base-collector junction. Also disclosed is a process and alternative process, for fabricating an improved bipolar transistor structure.

Process for fabricating a bipolar transistor

A semiconductor structure for, and method of manufacture of, a linear integrated circuit provides the equivalent of a base function in a transistor, wherein the base function has a dual charge density, with the latter being relatively low in the lower active area of the base between PN junctions for high gain and high breakdown voltage, but high along the upper surface to prevent an unwanted inversion layer from occurring.

Bruce C. Williams

Papers

High-gain, high-voltage transistor for linear integrated circuits