Multiprocessor system-on-chip (MPSoC) architectures have risen as a prevalent answer to the ever-increasing performance reduce the power consumption requirements, that are customized to a specific application have the potential to achieve efficient area, while additionally obliging low power consumption. The power consumed and area of the system majorly depends on the memory Communication medium of Processors, some issues involved in Memory communication of processors. In this Paper we avoid that issue and show two separate techniques to reduce the power consumption and area. The main technique is Scratch Pad Memory (SPM) replacement instead of cache replacement, second technique is Network on Chip (NOC) instead of Advanced Microcontroller Bus Architecture (AMBA) communication medium between processors.

Low-power and area efficient N-bit parallel processors on a chip

Advanced microcontroller bus architecture (AMBA) protocol family provides metric-driven verification of protocol compliance, enabling comprehensive testing of interface intellectual property (IP) blocks and system-on-chip (SoC) designs The AMBA advanced extensible interface 4 (AXI4) update to AMBA AXI3 includes the following: support for burst lengths up to 256 beats, updated write response requirements, removal of locked transactions and AXI4 also includes information on the interoperability of components AMBA AXI4 protocol system supports 16 masters and 16 slaves interfacing This paper presents a project aimed to do data transactions on SoC bus using AMBA AXI4 protocol modeled in Verilog hardware description language (HDL) and simulation results for read and write operation of data and address are shown in Verilog compiler simulator (VCS) tool The operating frequency is set to 100MHz Two test cases are run to perform multiple read and multiple write operations To perform single read operation module takes 160ns and for single write operation it takes 565ns

Data transactions on system-on-chip bus using AXI4 protocol

A globally asynchronous, locally synchronous clocking scheme for large-scale single flux quantum (SFQ) systems is proposed. In this scheme, the width of each data bus is extended to carry the corresponding clock signal. This signal activates the distribution of the clock signals within the receiving block. Based on this approach for intra-chip interconnect within SFQ systems, a configurable shared bus is also proposed. The data are attached to a tag, and a resulting data packet is sent to the shared bus. This packet is received by each block, but only processed if the tag matches the block identifier. By avoiding expensive comparators and multiplexers, the overhead of the global bus connection is reduced. The proposed approaches exploit the pulse-based nature and ambiguity of clock and data in SFQ technology – the data packet propagating through the interconnect carries a local clock signal.

Globally Asynchronous, Locally Synchronous Clocking and Shared Interconnect for Large-Scale SFQ Systems

Early estimation of the peak power consumption of a system under development is crucial in assessing the design’s thermal profile and reliability, and in benchmarking the chip-level power management features. In this paper, we present a high-level systematic methodology for generating the appropriate traffic patterns that trigger the peak power consumption in a network-on-chip (NoC), irrespective of the latter’s structural and functional properties. The generation of peak-power traffic is performed by solving a novel optimization problem based on integer linear programming, which models the traffic that can realistically flow in the network, thus avoiding any fake and pessimistic scenarios. This formulation can handle arbitrary network configurations and routing algorithms, including heterogeneous network topologies with multiple link widths and voltage/clock domains. The proposed technique maximizes both the network utilization and the data switching activity, thereby causing, on average, ${4 \times }$ higher power consumption than synthetic traffic patterns with random behavior. Most importantly, the proposed method reveals the realistic ceiling of the NoC’s peak power consumption, by reporting significantly lower peak power ( ${3\times }$ less), as compared to fake worst-case scenarios that can never, in fact, occur during the NoC’s normal operation.

Automatic Generation of Peak-Power Traffic for Networks-on-Chip

With the need of application, chip with a single processor can't meet the need of more and more complex computational task. We are able to integrate multiple processors on a chip. Multi Procesor System on Chip (MPSoC) which gives a solution to this requires efficient on-chip communication architectures to support high data bandwidth and increase parallelism. However, traditional buses only allow one master to access one slave at one time, which badly restricts the performance of the whole system. In this paper we focus on the design and implementation of a multi slave interface for AXI bus, which translates data in burst, maximal length of which is up to 16 transactions. Besides, it only needs to translate the head address of the burst in this transaction. Owing to that feature, multiple masters accessing multiple slaves at one time becomes possible in sharing address bus architecture.

Implementation of multi-slave interface for AXI bus

In this paper, we describe “The Evolution of SOC Interconnect and How NOC Fits Within It” which is being presented during the “A Decade of NOC Research — Where Do We Stand?” session at DAC 2010. The presentation looks at the features that have helped shape the development of on-chip interconnect solutions. The evolution of NoC is considered alongside the evolution of the AMBA on-chip communication architecture, and consideration is given to the techniques that are considered most important.

Bruce Mathewson

Papers

The evolution of SOC interconnect and how NOC fits within it