Kurskod: 5DV050 Inrättad: 2008-03-31 Inrättad av: teknisk-naturvetenskapliga fakultetsnämnden Reviderad: 2012-02-29 Reviderad av: teknisk-naturvetenskapliga fakultetsnämnden Kursplan giltig från: 2012, vecka 10 Ansvarig enhet: Inst för datavetenskap SCB-ämnesrubrik: Informatik/Dataoch systemvetenskap Huvudområden och successiv fördjupning: Beräkningsteknik: Avancerad nivå, har endast kurs/er på grundnivå som förkunskapskrav (A1N) , Datavetenskap: Avancerad nivå, har endast kurs/er på grundnivå som förkunskapskrav (A1N) Betygsskala: För denna kurs ges betygen 5 Med beröm godkänd, 4 Icke utan beröm godkänd, 3 Godkänd, VG Väl godkänd, G Godkänd, U Underkänd Utbildningsnivå: Avancerad nivå

The design and analysis of parallel algorithms

Image processing problems frequently involve large structured arrays of data and a need for very rapid computation. Special parallel processing schemes have evolved over the last 20 years to deal with these problems. In this paper many parallel systems which have been developed for image processing are outlined and the features of their underlying architectures are discussed. Most of these special architectures may be loosely classified as either SIMD or pipeline structures although some MIMD structures have been designed for high level image analysis. In recent years several multiple SIMD (MSIMD) schemes have been proposed as suitable architectures for image processing. The fundamental problems of developing an effective MSIMD system are discussed and a simple SIMD/MIMD computational model for comparison with such systems is proposed.

Parallel computer architectures for image processing

Computer architectures for image processing in the USA

Search algorithms for bi-sequential machines

The design and implementation of an integrated associative processor is described. The chip is intended for use as a coprocessor in a system for accelerating pixel-parallel image processing tasks on desktop workstations and personal computers. Each of the chip's 256 processing elements includes 64 trits of three-state memory, a function generator, an activity register, and connections to a reconfigurable mesh network and a response resolution subsystem. The device-intensive design style makes extensive use of dynamic logic in dense pitch-matched circuits.
A novel dynamic associative memory cell supports fully-parallel match and write operations. The cell uses five MOS transistors, including two overlapping dual-gate devices available in double-polysilicon processes. The necessary sense and driver circuits are discussed, with particular attention to switching noise considerations.
The processing elements communicate over an Asynchronous Reconfigurable Mesh network which provides a mechanism for simultaneous broadcasting over multiple connected regions. The area-efficient implementation requires only one driver circuit per processing element. The network is readily extendible across chip boundaries, so that large arrays can be constructed with multiple chips.
A new response resolution circuit is used to count and prioritize selected processing elements. A compact pass transistor chain is used within the confines of the array, and results from multiple arrays are combined in a tree structure.
Results are presented which verify the full functionality of all chip subsystems. The performance evaluation of the design is complicated by the fact that the chip was fabricated in a process other than that for which it was intended, but experimental results are shown to be consistent with measured process parameters. A 6-V supply is used to compensate for the high (2.1 V) second-polysilicon threshold voltages. Write and match instructions are performed in 175 ns, and 220 mW are dissipated in typical applications. The results of storage time experiments examining charge pumping, spooning, and leakage effects are presented.
A sample image processing application is demonstrated on a prototype system with four chips and 1024 processing elements. Several ideas for further work are discussed in the conclusion. (Copies available exclusively from MIT Libraries, Rm. 14-0551, Cambridge, MA 02139-4307. Ph. 617-253-5668; Fax 617-253-1690.)

An integrated associative processing system

Parallel processors with bit-serial processing elements (PE's) usually implement arithmetic functions by a sequence of word-level arithmetic operations; however, basic operations must be specified at the bit level. In this correspondence the possibility of more efficiently implementing a function with a special tailored sequence of bit-serial operations is considered. A general scheme is described for generating efficient programs to implement arbitrary functions on bit-serial-arithmetic processors. This scheme is based on logic design methodology and involves designing a logic network to realize a desired function. The parallel processor is then used to efficiently simulate a set of these networks. Heuristic design algorithms are used to generate the logic networks; several algorithms are described and compared with some benchmark functions. Several efficient PE designs are described and analyzed.

Bruner

Papers

Efficient Function Implementation for Bit-Serial Parallel Processors