We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ?W. The measured input-referred noise is 6.08 ? Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ?W. The design is implemented in 0.35-?m complementary metal-oxide semiconductor technology with the channel pitch of 200 ?m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg2+/high-K+ epileptic seizure model in an intact hippocampus of a mouse.

/pdf/the-128-channel-fully-differential-digital-integrated-neural-2de1s1iso7.pdf

The 128-Channel Fully Differential Digital Integrated Neural Recording and Stimulation Interface

We present a multichip structure assembled with a medical-grade stainless-steel microelectrode array intended for neural recordings from multiple channels. The design features a mixed-signal integrated circuit (IC) that handles conditioning, digitization, and time-division multiplexing of neural signals, and a digital IC that provides control, bandwidth reduction, and data communications for telemetry toward a remote host. Bandwidth reduction is achieved through action potential detection and complete capture of waveforms by means of onchip data buffering. The adopted architecture uses high parallelism and low-power building blocks for safety and long-term implantability. Both ICs are fabricated in a CMOS 0.18-mum process and are subsequently mounted on the base of the microelectrode array. The chips are stacked according to a vertical integration approach for better compactness. The presented device integrates 16 channels, and is scalable to hundreds of recording channels. Its performance was validated on a testbench with synthetic neural signals. The proposed interface presents a power consumption of 138 muW per channel, a size of 2.30 mm2, and achieves a bandwidth reduction factor of up to 48 with typical recordings.

A Mixed-Signal Multichip Neural Recording Interface With Bandwidth Reduction

Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

https://iopscience.iop.org/article/10.1088/1741-2560/6/1/012001/pdf

Integrated circuit amplifiers for multi-electrode intracortical recording.

This paper presents a neural recording amplifier array suitable for large-scale integration with multielectrode arrays in very low-power microelectronic cortical implants. The proposed amplifier is one of the most energy-efficient structures reported to date, which theoretically achieves an effective noise efficiency factor (NEF) smaller than the limit that can be achieved by any existing amplifier topology, which utilizes a differential pair input stage. The proposed architecture, which is referred to as a partial operational transconductance amplifier sharing architecture, results in a significant reduction of power dissipation as well as silicon area, in addition to the very low NEF. The effect of mismatch on crosstalk between channels and the tradeoff between noise and crosstalk are theoretically analyzed. Moreover, a mathematical model of the nonlinearity of the amplifier is derived, and its accuracy is confirmed by simulations and measurements. For an array of four neural amplifiers, measurement results show a midband gain of 39.4 dB and a -3-dB bandwidth ranging from 10 Hz to 7.2 kHz. The input-referred noise integrated from 10 Hz to 100 kHz is measured at 3.5 μVrms and the power consumption is 7.92 μW from a 1.8-V supply, which corresponds to NEF = 3.35. The worst-case crosstalk and common-mode rejection ratio within the desired bandwidth are - 43.5 dB and 70.1 dB, respectively, and the active silicon area of each amplifier is 256 μm × 256 μm in 0.18-μm complementary metal-oxide semiconductor technology.

Energy Efficient Low-Noise Neural Recording Amplifier With Enhanced Noise Efficiency Factor

This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR) The front-end circuit consisting of a preamplifier followed by a 6th-order bandpass filter is designed for signal sensing in a future epileptic deep brain stimulator A current-splitting technique is combined with an output-branch current scaling technique in a folded-cascode amplifier structure to improve the noise and power tradeoff in the preamplifier In measurements, the preamplifier exhibits 394 dB DC gain, 036 Hz to 13 kHz of -3 dB bandwidth, and 307 μVrms total input-referred noise while consuming 24 μW from a 28 V power supply provided by an on-chip regulator circuit A noise efficiency factor (NEF) of 309 is achieved with minimal power consumption and is one of the lowest published to date The 6th-order follow-the-leader feedback elliptic bandpass filter passes FR signals and provides -110 dB/decade attenuation to out-of-band frequency components In measurements, the entire front-end circuit achieves a mid-band gain of 385 dB, a bandwidth from 250 to 486 Hz, and a total input-referred noise of 248 μVrms while consuming 45 μW from the 28 V power supply The front-end NEF achieved is 76 To the authors' knowledge, the proposed epileptic seizure- detection system is the first to achieve the FR-recording functionality The chip is fabricated in a standard 06 μm CMOS process Die size is 045 mm2

A Micropower Low-Noise Neural Recording Front-End Circuit for Epileptic Seizure Detection

We present in this paper a low-power bioamplifier suitable for massive integration in dense multichannel recording devices. This bioamplifier achieves reduced-size compared to previous designs by means of active low-frequency suppression. An active integrator located in the feedback path of a low-noise amplifier is employed for placing a highpass cutoff frequency within the transfer function. A very long integrating time constant is achieved using a small integrated capacitor and a MOS-bipolar equivalent resistor. This configuration rejects unwanted low-frequency contents without the need for input RC networks or large feedback capacitors. Therefore, the bioamplifier high-input impedance and small size are preserved. The bioamplifier, implemented in a 0.18-mum CMOS process, has been designed for neural recording of action potentials, and optimised through a transconductance-ef-ficiency design methodology for micropower operation. Measured performance and results obtained from in vivo recordings are presented. The integrated bioamplifier provides a midband gain of 50 dB, and achieves an input-referred noise of 5.6 muVrms. It occupies less than 0.050 mm2 of chip area and dissipates 8.6 muW.

C.A. Chapman

Papers

A Low-Power Integrated Bioamplifier With Active Low-Frequency Suppression