Publisher Summary This chapter discusses the controversial claim that any continuous periodic signal could be represented by the sum of properly chosen sinusoidal waves. Fourier analysis forms the basis for much of digital signal processing. Simply stated, the Fourier transform (there are actually several members of this family) allows a time domain signal to be converted into its equivalent representation in the frequency domain. Conversely, if the frequency response of a signal is known, the inverse Fourier transform allows the corresponding time domain signal to be determined. In addition to frequency analysis, these transforms are useful in filter design, because the frequency response of a filter can be obtained by taking the Fourier transform of its impulse response. Conversely, if the frequency response is specified, the required impulse response can be obtained by taking the inverse Fourier transform of the frequency response. Digital filters can be constructed based on their impulse response, because the coefficients of an FIR filter and its impulse response are identical.

Fast Fourier Transforms

Convolution is an important mathematical tool in both fields of signal and image processing. It is em-ployed in filtering, denoising, edge detection, correlation, compression, deconvolution, simulation, and in many other applications. Although the concept of convolution is not new, the efficient computation of convolution is still an open topic. As the amount of processed data is constantly increasing, there is considerable request for fast manipulation with huge data. Moreover, there is demand for fast algorithms which can exploit computational power of modern parallel architectures. The aim of this chapter is to review the algorithms and approaches for computation of convolution with regards to various properties such as signal and kernel size or kernel separability (when pro-cessing n-dimensional signals). Target architectures include superscalar and parallel processing units (namely CPU, DSP, and GPU), programmable architectures (e.g. FPGA), and distributed systems (such as grids). The structure of the chapter is designed to cover various applications with respect to the signal size, from small to large scales.

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Algorithms for Efficient Computation of Convolution

The decimation-in-time radix-2, radix-4, split-ra- dix, and radix-8 algorithms, presented in a paper by Linzer and Feig (5), are described in detail. These algorithms compute discrete Fourier transforms (DFT's) on input sequences with lengths that are powers of 2 with fewer multiply-adds than tra- ditional Cooley-Tukey algorithms. The descriptions given pro- vide the needed details to implement these algorithms efficiently in a computer program that could compute DFT's on a length 2" sequence for general m. We describe and give timing results for a radix-4 version that we have implemented on the RS/6000 workstation. The timing results show that a substantial saving in execution time is obtained when the new radix-4 FFT is used instead of a standard Cooley-Tukey radix-4 FFT. Finally, we present a set of experiments that suggest that numerical behav- ior of the new algorithms is slightly better than the numerical behavior of Cooley-Tukey FFT's.

Implementation of Efficient FFT Algorithms on Fused Multiply- Add Architectures

A new algorithm for computing Hadamard transforms is presented. If n is a power of four, then the new algorithm uses 7/8 n log/sub 2/ n multiply/adds to compute a Hadamard transform of length n. >

Hadamard transforms on multiply/add architectures

A new class of FFT (fast Fourier transform) algorithms that run very efficiently on digital signal processors (DSPs) is described. The algorithms are based on a tensor product factorization of the DFT (discrete Fourier transform). The tensor product factorization not only controls the breakdown into short-length DFTs but also shows the data flow between the various blocks. This allows a better scheduling of operations, which again gives a better utilization of the DSP pipelining/parallel capabilities, and leads to algorithms with significantly lower overhead than traditional methods. Several different programs have been implemented in assembly code for the TMS320C30 and simulated to find their execution times. The new algorithms are shown to be more than 20% faster than traditional sequential algorithms adapted to the processor, because of lower overhead, and better utilization of the parallel instruction sets and the pipelining is obtained. >

Efficient FFT algorithms for DSP processors using tensor product decompositions

This paper develops an approach to deriving special FFT and convolution algorithms, considering the architecture of special-purpose DSP micros with a hardware multiplier and an adjacent accumulator. Because of the build-in accumulator, it is possible to combine multiplications and additions into one operation, and hence the optimality criterion is redefined to minimize the total number of additions, multiplications and combined multiply-additions, which results in new interesting algorithms. The structure of the algorithms depends strongly on the nature of N - the sequence length. Where most conventional fast algorithms decompose convolutions completely, it turns out that because the adjacent accumulator can hides some of the additions, they should only be partly decomposed. The decomposition is done by index mapping and the implementation uses Winograd's ideas. Discrete Fourier transforms are also only partly decomposed, in contrast to most algorithms. The DFTs are converted into convolutions, and the convolutions are implemented as block processing. Comparisons show up to a 35 % improvement in execution speed.

C. Burrus

Papers

FFT and convolution algorithms on DSP microprocessors