A multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The multiprocessor system includes several individual processors all having communication links to several memories. Additional instruction memories are dedicated individually as cache memories to particular processors so that the processors can function in the multiple instruction, multiple data (MIMD) mode. When the processors function in the single instruction, multiple data mode (SIMD) the dedicated memories are reassigned for access by all of the processors for data. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Dual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode

A multi-processor system arranged, in one embodiment, as an image and graphics processor The processor is structured with several individual processors all having communication links to several memories An addressing scheme, called sliced addressing, is used to spread contiguous related data over several memories so that the data can be concurrently accessed by several processors A crossbar switch serves to establish the processor memory links The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip

Sliced addressing multi-processor and method of operation

There is disclosed a multiprocessor system and method arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories without restriction. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories, are contained on a single silicon chip.

Multi-processor with crossbar link of processors and memories and method of operation

There is disclosed a switch matrix and operational method relying upon a high degree of operational logic at each matrix crosspoint In one embodiment, the switch is used in a multiprocessor system arranged as an image and graphics processor The processor is structured with several individual processors all having communication links to several memories without restriction The switch matrix serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories and is contained on a single silicon substrate

Switch matrix having integrated crosspoint logic and method of operation

In an imaging system (5310), a histogram of images may be made by counting the number of "one" pixels in a matrix of image pixels. A ones counting circuit (5320) is provided to produce a binary number Y indicative of the number of "ones" in an input binary string X. The circuit (5320) comprises a matrix (5424) of counting cells (5426) arranged and interconnected in rows and columns. Each of the counting cells (5426) includes an AND gate (5428) coupled to an exclusive-OR (XOR) gate (5430). A binary string having XN bits may be thus counted employing a matrix having M rows, where M=log2(XN +1) rounded up to the nearest integer and N columns. An alternative embodiment employs a minimized matrix. This minimized matrix has M rows, where M=log2(XN +1) rounded up to the nearest integer. The minimized matrix has N=XN -2r elements in each row, where r is the row number ranging from zero for the first row to (M-1) for the last row.

Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data

We describe a novel, expandable, multiple digital signal processor (DSP) architecture with a symbolic processing host. A multiprocessor board, called Odyssey, based on this architecture has been developed to combine symbolic and real-time digital signal processing in a single computing environment. Some of the key features of the board are: 20 million multiply/accumulates per second, 512K bytes of data space, and expandability to 16 boards on a NuBus host. The DSPs used are the TMS32020 signal processing chips developed by Texas Instruments, and the host is Texas Instruments' Explorer, a LISP machine workstation. This provides environment to perform many intelligent signal processing tasks by associating meaningful relationships between quantitative (signal processing) and qualitative (symbolic processing) entities to develop inferences using expert system technology. Applications such as grammar-driven connected speech recognition, neural network simulation, EEG analysis, and generation of speech from general English text with natural language processing are some of the tasks that can utilize the computational power of the multiple DSP and/or the associated symbolic processing capabilities. Software development tools to implement applications include the device driver to facilitate communication between the host processor and the Odyssey board, a unique window-based debugger resident on the Explorer that allows for simultaneous state display of all the processors on the board, a FORTH interpreter for high-level language programming, and a cross-assembler/linker for assembly level programming.

C.D. Covington

Papers

Multiple digital signal processor environment for intelligent signal processing