A highly linear programmable-gain amplifier (PGA) is fabricated using a 0.35-/spl mu/m CMOS technology. High linearity and constant wide bandwidth are achieved by using a high-gain amplifier with low input impedance and resistor-network feedback. The voltage gain is varied by digitally controlling the input switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is -86dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.

https://ir.nctu.edu.tw:443/bitstream/11536/27489/1/000185568500010.pdf

A highly linear 125-MHz CMOS switched-resistor programmable-gain amplifier

Among all noise sources present in wireline transmission systems we focus on one special type: narrowband radio frequency interference generated by radio amateurs (RAM) and broadcast radio stations. This disturbance, characterized by high power and narrow bandwidth, has the potential of overloading the receiver's analog-to-digital converter (ADC). Once the ADC is in saturation, any countermeasure taken in digital domain will fail. A viable way to face this problem is cancellation using the common-mode signal as a reference. This paper describes in detail an adaptive, mixed-signal, narrowband interference canceller employing a modified recursive least-squares algorithm, which is split into an analog and a digital part. The mixed-signal approach enables the circuit to generate an interference-cancelling signal of several MHz while operating the adaptive algorithm at some kilohertz. Simulation as well as measurement results show a steady-state disturbance suppression of about 35 dB. The convergence speed is high enough to protect the ADC from overloading due to time-variant HAM interference.

An approach to analog mitigation of RFI

In this work a high voltage line driver, using a self-oscillating power amplifier (SOPA) in a digital 1.2 V 0.13 /spl mu/m CMOS technology is presented. A self biasing cascode topology allows the line driver to operate at 4.5 times the nominal supply voltage. Oxide breakdown and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The realized prototype delivers a 35 MHz PWM square wave with a 4.6 V swing in a 7.1 /spl Omega/ load with an efficiency of 62%. The chip achieves a spurious free dynamic range (SFDR) of 52 dB while driving a 1 MHz sine wave. A missing tone power ratio (MTPR) of 50 dB has been measured for a DMT signal up to 1.1 MHz with a crest factor of 14 dB.

A 5.5 V SOPA line driver in a standard 1.2 V 0.13 /spl mu/m CMOS technology

Communication over the copper twisted-pair channel is performed by transmitting and receiving differential-mode (DM) signals. In this paper, we extend the conventional DM receiver scheme by incorporating the common-mode (CM) signal, which is strongly correlated with the DM signal and can be extracted at the end of every wire pair. The wireline channel, including the CM receive signal, is modelled as a Gaussian vector (multiple-input multiple-output) channel with memory and an arbitrary number of disturbers that introduce interference which can be correlated both temporally and spatially. We investigate the potential of CM-aided reception in terms of information rate for single-user digital subscriber line systems (xDSL) operating on a single pair. Numerical results of information rate calculations using measured channel data are presented. The achievable information rate of the twisted-pair channel when incorporating the CM signal in practically relevant example scenarios can exceed the information rate of the conventional DM channel by a factor of up to two. Copyright (C) 2005 AEIT. (Less)

Information rate bounds in common-mode aided wireline communications

An integrated transceiver for broadband wireline networks is presented. The transceiver includes a receive data path, a transmit data path, and auxiliary functions including serial port interface, clock and reference generation blocks, and voltage regulator control circuitry. The receive data path provides constant input impedance and is composed of two variable gain amplifier (VGA) blocks, a tuned analog 4-pole filter, a 12-b analog-to-digital converter (ADC) sampling at 32 MHz, and a digital high-pass filter. Filter tuning using switched-capacitor arrays occurs in the background, with no effect on signal reception. The transmit data path contains digital interpolation filters and a 12-b digital-to-analog converter (DAC) sampling at 128 MHz. The chip was implemented in double-poly triple-metal 0.35-/spl mu/m CMOS technology. Measured performance for both receive and transmit data paths meets target specifications with no noticeable crosstalk.

A 12-bit integrated analog front-end for broadband wireline networks

Digital subscriber loop (DSL) technology allows high-speed transmission between the telephone central office and subscriber premises using existing unshielded twisted-pair loop plant, coexisting with telephony Very-high-speed DSL (VDSL) is a new service aimed at loop lengths up to 3000 m, providing 2-52 Mb/s data The VDSL signal occupies the 02-11 MHz spectrum This IC provides the analog functions required in a VDSL modem that uses synchronized discrete multi-tone (SDMT) line code It is implemented in 035 /spl mu/m CMOS double-poly-triple-metal process and consumes 550 mW at 2208 MHz sample rate with a single 33 V supply The die measures 180/spl times/150 mil/sup 2/

C. Frost

Papers

An integrated analog front-end for VDSL