Empirical Mode Decomposition (EMD) is used to decompose the signal into its principal constituents called Intrinsic Mode Function (IMF). Although it is one of the most widely used research method with applications seen across number of fields, real-time hardware implementation of EMD is challenging due to its computational intensive loop structure. In this paper we propose a module based approach for hardware implementation of the EMD in FPGA. The proposed architecture uses hardware compatible stopping criteria and a way to mitigate end effects. Xilinx System Generator (XSG), a model based industry standard tool has been proposed to implement the architecture on Xilinx 7-series FPGA (XC7K325T-2FFG900C). Root mean square error of 2.35×10−4 to 2.597×10−4 and correlation coefficient of 0.9963 to 0.9981 has been observed for IMF 1 when compared with the Matlab simulation results.

Efficient implementation of empirical mode decomposition in FPGA Using Xilinx System Generator

Biopotential data measurement plays an important role in monitoring the body’s physiological functions. It is affected by noise from various sources for different signals adversely affecting the ability to interpret them. The traditional methods of data detrending are either computationally inefficient, power-intensive, or have high latency. The maximum–mean–minimum (MaMeMi) filter reported for electrocardiogram (ECG) denoising is a computationally efficient algorithm. The MaMeMi filter response depends on two filter coefficients. In the real time, it is difficult to gauge the characteristics of the detected signal beforehand. In this article, we propose an adaptive-MaMeMi (AMaMeMi) filter, which adaptively computes the filter coefficients according to the properties of the input. We have used hardware–software codesign techniques for the optimized implementation of the AMaMeMi filter. The proposed hardware accelerator architecture for the AMaMeMi filter can be used in both adaptive and manual modes of operation. The hardware accelerator is tested for various biopotential signal detrendings, and the single hardware is capable of eliminating baseline wander from all considered measurements with less computational costs and low latency. We implemented the AMaMeMi filter on Xilinx Zynq-7000 system-on-chip (part number XCZ7020-CLG484-1) and statistically verified the results. The hardware accelerator implementation results provide a good correlation with MATLAB simulation results. The hardware accelerator implementation provides an average correlation of 0.9999, a normalized root-mean-square error of 0.0038, and a maximum signal-to-noise ratio (SNR) gain of 19 dB. The low computational complexity of the proposed architecture implies low-power consumption. It consumes 12 mW at 100-MHz clock and 0.7 mW at 500-Hz clock.

Low-Power Hardware Accelerator for Detrending Measured Biopotential Data

Very Large Scale Integration (VLSI) design is a technological advancement in electronics that has widely shortened the window from concept to a working prototype in any design. It has also made it possible to design and develop sophisticated and intelligent electronic systems which are easily adaptable to any field of human endeavor with relative ease. In this paper, the VLSI design of a processor system is presented, which implements two transforms i.e. the discrete wavelet packet, and the Hilbert transforms. The combination of these two transforms in a single processor makes it possible to have a system with enhanced subband frequency edge detection in a wideband signal and other specialized areas, which is very useful in such specialized areas of application as spectrum sensing in cognitive radio networks. The results obtained from the simulation and design verification of the processor system showed the effectiveness of the design methodology presented in this paper. As a matter of fact, the arithmetic operators designed in this paper outperformed the arithmetic operators of the Xilinx IP CORE when compared in terms of speed. From the results obtained, it was clear that the processor design performed as expected, at a great speed.

VLSI Design of a Processor for Discrete Wavelet Packet and Hilbert Transforms

Single-photodiode-per-polarization coherent receivers (SCRs) can preserve all of the merits of the conventional digital coherent receivers (DCRs) such as supporting chromatic dispersion (CD) compensation and polarization multiplexing, whilst have much lower optical complexity. But the overall algorithm complexity of the SCRs is relatively higher because an extra dedicated field reconstruction algorithm (FRA) is required in addition to the standard algorithms used in DCRs. The heavy computation burden introduced by the FRA poses a major obstacle to reduce the DSP chip size and power consumption. In this paper we propose a method to reduce the overall algorithm complexity of the SCR by utilizing several techniques, including utilizing a strong local oscillator (LO) to mitigate the signal-signal beat interference (SSBI), a pseudo-single-side-band signal to recovery the signal field and a new FRA to reuse the operations in the CD compensation algorithm to realize field reconstruction. Other than reducing the overall algorithm complexity, the new method also make the SCR more robust to laser frequency offset compared with the existing heterodyne detection based FRA. Numerical simulations and experiments are presented to demonstrate the merits of new method with respect to the existing ones.

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A Method to Reduce the Algorithm Complexity of the Single-Photodiode-per-Polarization Coherent Receiver

The presented work demonstrates the most suitable architecture for the FPGA-based signal processing which makes available various real-time filtering algorithms, such as band pass, high pass, low pass, and band-reject for FIR filters. The processor was implemented with the fixed-point arithmetic using VHDL, which can be downloadable on FPGA device. The FPGA device can be interfaced with an analog-to-digital converter (ADC), digital-to-analog converter (DAC) and a personal computer with MATLAB for the user interface and feeding coefficients and order of the filter. The core part of this paper was to find the reconfigurable and efficient architecture of the processor with only one multiplier which can work for Finite Impulse response (FIR) filter with the best- suited structure. The system will be used for automatic generation of fixed-point FIR filters. The model was also implemented in MATLAB script and the verification of results in the case of low-pass filtering confirmed that both models in MATLAB and VHDL matched to each other. All components of architecture in VHDL were designed using generics which allow changing its structure and behavior by generic values. Therefore, it is a universal filter platform where user can process the data while changing the filter parameters as per the requirement of applications. The complete design was verified by taking the example of audio signal frequency, but parameterized components of system architecture can also facilitate its applicability at ultrasonic frequencies by changing the algorithm. The significance and applicability of FPGAs in ultrasonic signal processing were also studied and reviewed.

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Efficient FPGA-based FIR – architecture and its significance in ultrasonic signal processing

This paper presents an architecture for real time hardware implementation of Hilbert Transform (HT) using Fast Fourier Transform (FFT). HT is studied and its various application areas are discussed in the paper. Two different architectures are proposed using Fast Fourier Transform (FFT) for the implementation. Implementation of HT using the proposed FFT based architectures are compared with the implementations using Discrete Fourier Transform (DFT) and Discrete Hartley Transform (DHT). The proposed FFT based architectures are implemented on Xilinx Kintex- 7 based FPGA and the results acquired are presented in comparison to results obtained through MATLAB simulations. The architecture implemented supports transform length of 8192 points as a demonstrator to the idea using 24 bit fixed point arithmetic. Detailed comparison study in terms of resource utilization and timing analysis is also carried out and the results are reported.

C. Jayakumar

Papers

Efficient architecture for real time implementation of Hilbert Transform in FPGA