One of the main advantages of class E amplifiers for RF and microwave applications relies on the inclusion of a shunt capacitance in the tuned output network. At high frequencies, this capacitance is mainly provided by the output parasitic capacitance of the device with perhaps a linear external one for fine adjustments. The device's output capacitance is nonlinear and this influences the design parameters, frequency limit of operation, and performance of the class E amplifier. This paper presents a design method for the class E amplifier with shunt capacitance combining a nonlinear and linear one for any duty cycle, any capacitance's nonlinear dependence parameters, and any loaded quality factor of the tuned network. Nonlinear design with possibly different duty cycles is of relevance to maximize power or, alternatively, frequency utilization of a given device. Experimental, simulated, and compared results are presented to prove this design procedure

Design of Class E Amplifier With Nonlinear and Linear Shunt Capacitances for Any Duty Cycle

The Class E amplifier requires exact shunt capacitance to achieve optimum operation. Most Class E amplifiers are usually constructed by adding an external capacitor to the output capacitance of the power transistor in order to obtain the total required shunt capacitance. The output capacitance of the power transistor is nonlinear and the external capacitance is linear. Therefore, neither design equations for linear shunt capacitance nor the design equations for nonlinear shunt capacitance can be used in most designs, especially when the two are comparable. This paper presents an analysis and a design procedure for the Class E amplifier with a shunt capacitance composed of both a transistor nonlinear output capacitance and a linear external capacitance for the duty cycle D=0.5. Because the design equations do not have analytical forms, this paper provides a table and figures, which show results of numerical analysis. The Class E amplifier can be designed using these table and figures. A design example is given to illustrate the design procedure. Simulation results of the example circuit with PSpice and experimental results are presented to verify the theoretical results.

Analysis and design of class E amplifier with shunt capacitance composed of nonlinear and linear capacitances

Comparison of class-E amplifier with nonlinear and linear shunt capacitance

Comparison of various parameters of the class-E amplifier with nonlinear and linear shunt capacitance is given. A concept of an equivalent linear shunt capacitance is introduced. The following parameters are compared for the amplifiers with nonlinear and linear shunt capacitance at the duty cycle D=0.5: series reactance, peak switch voltage, and power capability. A design procedure for the class-E amplifier with a nonlinear shunt capacitance is presented. Simulation of the designed class-E amplifier is performed to verify the design equations that ensure zero-voltage-switching operation.

A methodology for the optimal parasitic-aware design of RF power amplifiers toward maximum power efficiency is presented. It is based on a template-driven simulation-based optimization approach, including the effect of all device parasitics (transistors, passives) during the sizing. The combination of expert knowledge (in the template) with a state-of-the-art evolutionary algorithm results in a highly flexible and optimal sizing methodology tailored to RF circuits. Parasitic information is obtained through interaction with device profilers. The methodology is implemented in a fully featured software tool called M-DESIGN and is applied to the optimal sizing of a two-stage Class E power amplifier for maximum efficiency. The complete sizing was obtained in less than one hour of CPU time. Moreover, the constraint templates that were used are presented and discussed. An amplifier manufactured in a commercial 0.35-/spl mu/m 5M2P CMOS process and sized using the proposed methodology shows a maximum value of 67% for the drain efficiency (DE) versus 66% simulated. Measurement results show that it works at 850 MHz and has a maximum output power of 30 dBm at 2.3 V. The power-added efficiency (PAE) is always greater than 60% for an output power above 160 mW and a maximum PAE of 66% is achieved.

An efficient, fully parasitic-aware power amplifier design optimization tool

A numerical method for designing a class E power amplifier with a non-linear transistor output capacitance is presented. By matching the fundamental and second harmonic impedances of the output network, the method can be extended for designing a class E power amplifier with both non-linear transistor output capacitance and finite DC-feed inductance. A design example of 0.4 W 1.4 V class E power amplifier at 1 GHz with AMS 0.6 /spl mu/m BSIM.3v3 CMOS model is used to validate the method.

C.K.T. Chan

Papers

Design of a class E power amplifier with non-linear transistor output capacitance and finite DC-feed inductance