Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SoC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SoC as well as an industrial SoC.

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Test wrapper and test access mechanism co-optimization for system-on-chip

This paper presents the ITC'02 SOC test benchmarks. The purpose of this new benchmark set is to stimulate research into new methods and tools for modular testing of SOCs and to enable the objective comparison of such methods and tools with respect to effectiveness and efficiency. The paper defines the benchmark format and naming scheme, and presents the benchmark SOCs. In addition, it provides an overview of the research problems that can be addressed and evaluated by means of this benchmark set. These research problems include the design of optimized test access infrastructures and test schedules.

A set of benchmarks for modular testing of SOCs

The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and exhaustive enumeration. However, this approach is computationally expensive for large SOCs, and it is limited to fixed-width test buses. We present a new approach for wrapper/TAM co-optimization based on generalized rectangle packing, also referred to as two-dimensional packing. This approach allows us to decrease testing time by reducing the mismatch between a core's test data needs and the width of the TAM to which it is assigned. We apply our co-optimization technique to an academic benchmark SOC and three industrial SOCs. Compared to the ILP-based technique, we obtain lower or comparable testing times for two out of the three industrial SOCs. Moreover, we obtain more than two orders of magnitude decrease in the CPU time needed for wrapper/TAM co-design.

On using rectangle packing for SOC wrapper/TAM co-optimization

Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

A method to solve the resource allocation and test scheduling problems together in order to achieve concurrent test for core-based system-on-chip (SOC) designs is presented in this paper. The primary objective for concurrent SOC test is to reduce test application time. The methodology used in this paper is not limited to any specific test access mechanism (TAM). Additionally, it can also be applied for test budgeting during the design phase to obtain a tradeoff between test application time and SOC pins needed. In this paper, the above problem is formulated as a well-known 2-dimensional bin-packing problem. A best fit heuristic algorithm is employed to obtain satisfactory results.

Resource allocation and test scheduling for concurrent test of core-based SOC design

We present an optimization method that complies with IEEE P1500 draft standard and deals with modeling and design of the test access mechanism for the SoCs. The basic goal is to develop a global design for the test methodology and optimization technique for testing a core-based SoC in its entirety. We propose an ILP formulation to minimize the hardware cost or the overall access time which also produces the test access schedule.

C. Papachristou

Papers

An ILP formulation to optimize test access mechanism in system-on-chip testing