Digital image authentication is an extremely significant concern for the digital revolution, as it is easy to tamper with any image. In the last few decades, it has been an urgent concern for researchers to ensure the authenticity of digital images. Based on the desired applications, several suitable watermarking techniques have been developed to mitigate this concern. However, it is tough to achieve a watermarking system that is simultaneously robust and secure. This paper gives details of standard watermarking system frameworks and lists some standard requirements that are used in designing watermarking techniques for several distinct applications. The current trends of digital image watermarking techniques are also reviewed in order to find the state-of-the-art methods and their limitations. Some conventional attacks are discussed, and future research directions are given.

https://www.mdpi.com/2078-2489/11/2/110/pdf

Digital Image Watermarking Techniques: A Review

The transfer of medical images between hospitals is become a normal exercise for better decision making. Digital watermarking has played a very significant role in medical sciences for diagnosis and medication to protect reliability, availability, and confidentiality. Several methods are proposed for medical images using the spatial and transform domain. However, the data falsification ratio is high in the existing mechanisms while exchanging medical images. Hence, we suggest a wavelet based digital watermarking scheme for medical images using three level DWT and BCH coding, which can be used to the medical practitioners for accurate decisions. Security analysis of our proposed work has been done for security assessment, and performance results are discussed to confirm its implementation feasibility in medical sector.

Wavelet Based Digital Watermarking Scheme for Medical Images

Data security has become a major concern of present time. Digital image watermarking is seen as a viable solution to ensure the integrity of image data. Watermarking algorithms can detect the presence of various attacks on images. In this work, a secure and efficient fragile image watermarking technique is proposed. The proposed watermarking algorithm aims to find image tampering and its location. The proposed approch is a spatial domain, block-based embedding technique. It introduces a unique key based embedding using SHA-1 (Secure Hashing Algorithm) hashing. The watermarked images have high PSNR and SSIM. The algorithm can handle various size of tampering, from very small to large. The proposed technique has been tested for a wide variety of tampering attacks like copy-paste, copy-move, constant average, and general tampering. It can efficiently detect tampering in the presence of these attacks.

A secure image watermarking for tamper detection and localization

An efficient image encryption technique based on two-level security for internet of things

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, micro processors and digital signal processors etc. A system's performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the whole system and also it is occupying more area consuming. The Carry Select Adder (CSLA) provides a good compromise between cost and performance in carry propagation adder design. A Square Root Carry Select Adder using RCA is introduced but it offers some speed penalty. However, conventional CSLA is still area-consuming due to the dual ripple carry adder structure. In the proposed work, generally in Wallace multiplier the partial products are reduced as soon as possible and the final carry propagation path carry select adder is used. In this paper, modification is done at gate level to reduce area and power consumption. The Modified Square Root Carry Select-Adder (MCSLA) is designed using Common Boolean Logic and then compared with regular CSLA respective architectures, and this MCSLA is implemented in Wallace Tree Multiplier. This work gives the reduced area compared to normal Wallace tree multiplier. Finally an area efficient Wallace tree multiplier is designed using common Boolean logic based square root carry select adder.

Modified wallace tree multiplier using efficient square root carry select adder

Multimedia technology usages is increasing day by day and to provide authorized data and protecting the secret information from unauthorized use is highly difficult and involves a complex process. By using the watermarking technique, only authorized user can use the data. Digital watermarking is a widely used technology for the protection of digital data. Digital watermarking deals with the embedding of secret data into actual information. Digital watermarking techniques are classified into three major categories, and they were based on domain, type of document (text, image, music or video) and human perception. Performance of the watermarked images is analysed using Peak signal to noise ratio, mean square error and bit error rate. Watermarking of images has been researched profoundly for its specialized and modern achievability in all media applications such as copyrights protection, medical reports (MRI scan and X-ray), annotation and privacy control. This paper reviews the watermarking technique and its merits and demerits.

Digital watermarking techniques for image security: a review

Carry select adder (CSLA) is known to be the fastest adder among the conventional adder structures. Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which replaces the BEC using D latch. Experimental results are compared and the result analysis shows that the proposed architecture achieves the three folded advantages in terms of area, delay and power.

An efficient CSLA architecture for vlsi hardware implementation

Truncated multipliers offers significant improvements in area, delay, and power. The proposed method finally reduces the number of full adders and half adders during the tree reduction. While using this proposed method experimentally, area can be saved. The output is in the form of LSB and MSB. Finally the LSB part is compressed by using operations such as deletion, reduction, truncation, rounding and final addition. In previous related papers, to reduce the truncation error by adding error compensation circuits. In this project truncation error is not more than 1 ulp (unit of least position). So there is no need of error compensation circuits, and the final output will be precised.

Design and implementation of truncated multipliers for precision improvement

Reconfigurable system uses bitstream compression to reduce the bitstream size and the memory requirement. The communication bandwidth is improved by reducing the reconfiguration time. Existing research has explored efficient compression with slow decompression or fast decompression at the cost of compression efficiency. This paper proposes a decode-aware compression technique to improve both compression and decompression efficiencies. The three major contributions of this paper are: i) Efficient bitmask selection technique that can create a large set of matching patterns; ii) Proposes a bitmask based compression using the bitmask and dictionary selection technique that can significantly reduce the memory requirement iii) Efficient combination of bitmask-based compression and run length encoding of repetitive patterns. The original bitstream can be generated using the decompression engine.

Compression and decompression of FPGA bitstreams

Reconfigurable system uses bit-stream compression to reduce the bit-stream size and the memory requirement. The communication bandwidth is improved reducing the reconfiguration time. Existing research has explored efficient compression with slow decompression or fast decompression at the cost of compression efficiency. This paper proposes a decode- aware compression technique to improve both compression and decompression efficiencies. The three major contributions of this paper are: i) Efficient bitmask selection technique that can create a large set of matching patterns; ii) Proposes a bitmask based compression using the bitmask and dictionary selection technique that can significantly reduce the memory requirement iii) Efficient combination of bitmask-based compression and run length encoding of repetitive patterns.

C. S. Manikandababu

Papers

Digital watermarking techniques for image security: a review

An efficient CSLA architecture for vlsi hardware implementation

Design and implementation of truncated multipliers for precision improvement

Compression and decompression of FPGA bitstreams

FPGA Bit-stream Compression Using Run-length Encoding