The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then shows the architecture for a 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra. The paper then extends multiplication to 16×16 Vedic multiplier using "Nikhilam Sutra" technique. The 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8×8 Vedic multiplier modules; one 16 bit carry save adders, and two 17 bit full adder stages. The carry save adder in the multiplier architecture increases the speed of addition of partial products. The 16×16 Vedic multiplier is coded in VHDL, synthesized and simulated using Xilinx ISE 10.1 software. This multiplier is implemented on Spartan 2 FPGA device XC2S30-5pq208. The performance evaluation results in terms of speed and device utilization are compared with earlier multiplier architecture. The proposed design has speed improvements as compared to multiplier architecture presented in [5].

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Speed Comparison of 16x16 Vedic Multipliers

This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.

Area efficient modified vedic multiplier

This paper briefly describes the Urdhva-Tiryagbhyam Sutra of vedic mathematics and we have designed multiplier based on the sutra. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras which are discovered by Sri Bharti Krishna Tirthaji. In this era of digitalization, it is required to increase the speed of the digital circuits while reducing the on chip area and memory consumption. In various applications of digital signal processing, multiplication is one of the key component. Vedic technique eliminates the unwanted multiplication steps thus reducing the propagation delay in processor and hence reducing the hardware complexity in terms of area and memory requirement. We implement the basic building block: 16 × 16 Vedic multiplier based on Urdhva-Tiryagbhyam Sutra. This Vedic multiplier is coded in VHDL and synthesized and simulated by using Xilinx ISE 10.1. Further the design of array multiplier in VHDL is compared with proposed multiplier in terms of speed and memory.

Design and implementation of 16 × 16 multiplier using Vedic mathematics

The speed of a multiplier is of utmost importance to any Digital Signal Processor (DSPs). Along with the speed its precision also plays a major role. Although Floating point multipliers provide required precision they tend to consume more silicon area and are relatively slower compared to fixed point (Q-format) multipliers. In this paper we propose a method for fast fixed point signed multiplication based on Urdhava Tiryakbhyam method of Vedic mathematics. The coding is done for 16 bit (Q15) and 32 bit (Q31) fractional fixed point multiplications using Verilog and synthesized using Xilinx ISE version 12.2. Further the speed comparison of this multiplier with normal booth multiplier and Xilinx LogiCore parallel multiplier Intellectual Property (IP) is presented. The results clearly indicate that Urdhava Tiryakbhyam can have a great impact on improving the speed of Digital Signal Processors.

High speed signed multiplier for Digital Signal Processing applications

Now days most of the circuits which are going to be designed to perform any specific or safety critical operations are mainly based upon the digital domain, where microprocessors and microcontrollers plays an important role to design these digital circuits ALU is the heart of these processors By optimizing this co-processor a highly efficient digital processor can be obtained So this paper is totally devoted to design speed, energy and power efficient Arithmetic Logic Unit Speed of ALU is greatly depends upon the speed of multiplication unit There are so many multiplication techniques have been devised at algorithmic and structural level After a thorough study and deep analysis we have found that Vedic Urdhva Triyambakam multiplication algorithm is the best algorithm as it generates partial products in the parallel manner In this paper we have proposed a new tree multiplication structure based architecture to design this Vedic multiplier To generate partially generated products divide and conquer approach has been used For the addition of partially generated products a new addition tree structure has been proposed It provides better speed in comparison Array, Booth, Wallace, Modified Booth Wallace, Karatsuba and Vedic Karatsuba Multiplier as well as it is faster than Vedic multiplier which has been proposed by L Shriraman [2], and Devika Jaina [3] To make ALU energy and power efficient, a new reversible logic gate has been proposed which is similar to Fredkin Gate [18] After integrating these modules we have obtained the speed, energy and power efficient ALU The proposed Arithmetic Logic Unit is coded in Verilog HDL, synthesized and simulated using Xilinx ISE 92i software

Design of speed, energy and power efficient reversible logic based vedic ALU for digital processors

In this paper, a novel multiplier architecture based on ROM approach using Vedic Mathematics is proposed. This multiplier's architecture is similar to that of a Constant Coefficient Multiplier (KCM). However, for KCM one input is to be fixed, while the proposed multiplier can multiply two variables. The proposed multiplier is implemented on a Cyclone III FPGA, compared with Array Multiplier and Urdhava Multiplier for both 8 bit and 16 bit cases and the results are presented. The proposed multiplier is 1.5 times faster than the other multipliers for 16x16 case and consumes only 76% area for 8x8 multiplier and 42% area for 16x16 multiplier.

C. Sheshavali

Papers

Design and Implementation of Vedic Multiplier