Concurrent system-level error detection techniques using a watchdog processor are surveyed. A watchdog processor is a small and simple coprocessor that detects errors by monitoring the behavior of a system. Like replication, it does not depend on any fault model for error detection. However, it requires less hardware than replication. It is shown that a large number of errors can be detected by monitoring the control flow and memory-access behavior. Two techniques for control-flow checking are discussed and compared with current error-detection techniques. A scheme for memory-access checking based on capability-based addressing is described. The design of a watchdog for performing reasonable checks on the output of a main processor by executing assertions is discussed. >

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Concurrent error detection using watchdog processors-a survey

Software safety issues become important when computers are used to control real-time, safety-critical processes. This survey attempts to explain why there is a problem, what the problem is, and what is known about how to solve it. Since this is a relatively new software research area, emphasis is placed on delineating the outstanding issues and research topics.

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Software safety: why, what, and how

Pipelined computer architecture has received considerable attention since the 1960s when the need for faster and more cost-effective systems became critical. The merit of pipelining is that it can help to match the speeds of various subsystems without duplicating the cost of the entire system involved. As technology evolves, faster and cheaper LSI circuits become available, and the future of pipelining, either in a simple or complex form, becomes more promising.This paper reviews the many theoretical considerations and problems behind pipelining, surveying and comparing various representative pipeline machines that operate in either sequential or vector pipeline mode, the practical solutions adopted, and the tradeoffs involved. The performance of a simple pipe, the physical speed limitation, and the control structures for penalty-incurring events are analyzed separately. The problems faced by the system designers are tackled, including buffering, busing structur, branching, and interrupt handling. Aspects of sequential and vector processing are studied. Fundamental advantages of vector processing are unveiled, and additional requirements (costs) are discussed to establish a criterion for the tradeoff between sequential and vector pipeline processing. Finally, two recent machines (the CRAY-1 and the Amdahl 470 V/6 systems) are presented to demonstrate how complex pipeline techniques can be used and how simple but advantageous pipeline concepts can be exploited.

Pipeline Architecture

A control flow checking scheme capable of detecting control flow errors of programs resulting from software coding errors, hardware malfunctions, or memory mutilation during the execution of the program is presented. In this approach, the program is partitioned into loop-free intervals and a database containing the path information in each of the loop-free intervals is derived from the detailed design. The path in each loop-free interval actually traversed at run time is recorded and then checked against the information provided in the database, and any discrepancy indicates an error. This approach is general, and can detect all uncompensated illegal branches. Any uncompensated error that occurs during the execution of a loop-free interval and manifests itself as a wrong branch within the loop-free interval or right after the completion of execution of the loop-free interval is also detectable. The approach can also be used to check the control flow in the testing phase of program development. The capabilities, limitations, implementation, and the overhead of using this approach are discussed.

An Approach to Concurrent Control Flow Checking

Fault-tolerant software

Fault Tree Analysis (FTA) is a well developed technique for the reliability and safety analysis of complex systems such as nuclear power plants and weapon systems. In this paper, we apply FTA to analyze the reliability and the performance of computer systems. An approach to detect the sequence dependent faults in computer systems is proposed and exemplified. Based on the fault tree analysis, guidelines for up-grading the system can be developed.

Fault tree analysis of computer systems

The state-of-art in software validation as well as the continuing growth of the size and complexity of software subsystems, makes extra costs paid for software error tolerance more than justified. A program in which software redundancy is incorporated i.e. a program in which procedures for run-time validation and recovery are explicitly specified, is generally called a failure-tolerant program. One problem in failure-tolerant programming, which could be particularly serious in real-time computing environments, is the program execution time increased due to incorporation of validation and recovery procedures. This paper introduces an approach to the solution, called the failure-tolerant parallel programming. The essence of this approach is to maximally overlap main-stream computation with redundant computation oriented for validation and recovery. Subsequently, a model system architecture tailored for efficient execution of failure-tolerant parallel programs is described. It is of highly general and modular nature and contains a novel memory subsystem named the duplex memory. Directions of further researches on program structuring and expansion of the model architecture are also indicated.

Failure-tolerant parallel programming and its supporting system architecture

In this paper, we generalize the concept of pipelining to increase throughput, processing speed, resource utilization and reliability. Its wide application spectrum is demonstrated and major design problems such as sequencing, reconfiguration, etc., are indicated. A scheme called the dynamic sequencing and segmentation model (DSSM) is proposed as a solution for providing efficient sequencing with very low overhead. The model is analyzed under various realistic environments and its performance is evaluated.

Pipelining: the generalized concept and sequencing strategies

A common architecture of most of today's super machines revolves around parallel or pipeline processing. Typical examples of such machines are the CDC STAR-100, TI-ASC, PEPE, IBM 360/91, 360/195, and CDC 6600, 7600, etc. They all have distinct pipeline processing capabilities, either in the form of internally pipelined arithmetic functional units or in the form of a pipeline of special purpose functional units. The principal idea behind pipelining is to create as much overlap as possible in the operations of the different facilities, for example, memory fetch unit, decoding units, adders, and multipliers. Concurrency of different operations increases the system utilization. As an important consequence of concurrency, the execution speed of most jobs are accelerated considerably as is evidenced in systems like 360/195 and TI-ASC. Ideally, in a pipelined machine, instead of obtaining one output per major cycle from the system, a rate of one output per minor cycle may be achievable. A typical linear pipeline is as drawn in Figure 1(a).

C. V. Ramamoorthy

Papers

Fault tree analysis of computer systems

Failure-tolerant parallel programming and its supporting system architecture

Pipelining: the generalized concept and sequencing strategies

Efficiency in generalized pipeline networks

Pipelining- The generalized concept and sequencing strategies