In the beginning of this millennium power density and related heating problems practically stopped the exponential frequency increase of single core processors and limited availability of instruction-level parallelism (ILP) in general purpose applications started to limit the speedup achievable by increasing the number of simultaneously executed instructions in superscalar processors that along with architectural improvements in exploitation of memory hierarchies used to roughly duplicate the performance of processors in every second year for decades. In order to be able to continue the increasing trend of computational performance, all major processor manufacturers have switched to chip multiprocessors (CMP) integrating multiple processor cores on a single chip and switching the focus of parallelism from ILP to thread-level parallelism (TLP), because the number of transistors per chip still tends to increase exponentially with every new generation of silicon technology (ITRS, 2007) and high amounts of TLP is easier to extract than ILP. Manufacturers have ambitious plans to continue this development by roughly duplicating the number of cores per chip every second year, resulting to constellations with over 100 cores in ten years (Intel, 2006). This will, however, not happen without problems, because current CMP architectures and related programming models do not support simple migration to parallel computing, so called automatic parallelization of existing sequential code has been turned out to be extremely difficult for general purpose programs, writing explicitly parallel versions of programs has turned out to be tedious, error-prone and expensive, and achieving linear speed-ups with respect to the number of cores appears to be limited to only small classes of well-behaving algorithms. These problems are caused by inability of current architectures to hide the latency of shared memory accesses (or intercommunication), lack of synchronicity in execution of computational threads as well as too weak models and low-level primitives of parallel computing forcing a programmer to explicitly take care of data partitioning to maximize locality, functionality mapping supporting data partitioning, synchronization of subtasks, and communication. Without solving these problems, it is hard to imagine that parallel computing would be able to 3

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TOTAL ECLIPSE: An Efficient Architectural Realization of the Parallel Random Access Machine

Current communication protocols used for Wireless Sensor Networks (WSNs) have been designed to be energy efficient, low redundancy in sensed data, and long network lifetime. One major issue that must be addressed is the security of data communication. Due to the limited capabilities of sensor nodes, designing security-based communication protocols present a difficult challenge. Since commonly used encryption schemes require high time complexity and large memory, achieving security for WSNs needs unique approaches. In this paper, we consider a heterogeneous wireless sensor network (HWSN), where while most nodes are resource limited a few nodes can have more energy, stronger processing capability and longer communication range and can be used to relax the resource bottleneck. We propose a joint design approach that can best use the benefit that a HWSN brings. We first design a reconfigurable hierarchical networking architecture, where the HWSN is divided by the high-end nodes into regions, the low-end nodes in each region are divided by clusters, and high-end nodes and cluster heads form a communication/relay backbone. We then design a key management system that uses both public and symmetric key cryptography above the hierarchical networking architecture which requires very small number of security keys. The evaluation and simulation results show that by using the proposed networking architecture and key management scheme only a small amount of keys needs to be preloaded before deployment and stored after key setup to achieve secured communication throughout the entire network.

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Joint Design of Cluster-Based Hierarchical Networking Architecture and Key Management System for Heterogeneous Wireless Sensor Networks

Shortest-linkage-based parallel hierarchical clustering on main-belt moving objects of the solar system

Amdahl’s law, imposing a restriction on the speedup achievable by a multiple number of processors, based on the concept of sequential and parallelizable fractions of computations, has been used to justify, among others, asymmetric chip multiprocessor architectures and concerns of “dark silicon”. This paper demonstrates flaws in Amdahl’s law that (i) in theory no inherently sequential fractions of computations exists (ii) sequential fractions appearing in practice are inherently different from parallelizable fractions and therefore usually have different growth rates and that (iii) the time requirement of sequential fractions can be proportional to the number of processors. However, mathematical analyses are also provided to demonstrate that sequential fractions have negligible effect on speedup if the growth rate of the parallelizable fraction is higher than that of the sequential fraction. Examples from computational geometry are given that Amdahl’s law and its variants fail to represent limits to parallel computation. In particular, Gustafson’s law, claimed to be a refutation of Amdahl’s law by some authors, is shown to contradict established theoretical results. We can conclude that no simple formula or law governing concurrency exists.

The Refutation of Amdahl's Law and Its Variants.

P-complete problems seem to have no parallel algorithm which runs in polylogarithmic time using a polynomial number of processors. A P-complete problem is in class EP (Efficient and Polynomially fast) if and only if there exists a cost optimal algorithm to solve it in T(n) = O(t(n))Ɛ) (Ɛ>1) using P(n) processors such that T(n) × P(n) = O(t(n)), where t(n) is the time complexity of the fastest sequential algorithm which solves the problem. The goal of our research is to find EPparallel algorithms for P-complete problems. In this paper we consider two P-complete geometric problems in the plane. First we consider the convex layers problem of a set S of n points. Let k be the number of the convex layers of S. When 1 ≤ k ≤ nƐ/2 (0 < Ɛ < 1) we can find the convex layers of S in O( nlogn/p) time using p processors, where 1 ≤ p ≤ n1-Ɛ/2. Next, we consider the envelope layers problem of a set S of n line segments. Let k be the number of the envelope layers of S. When 1 ≤ k ≤ nƐ/2 (0 < Ɛ < 1), we propose an algorithm for computing the envelope layers of S in O( nα(n) log3 n/p) time using pprocessors, where 1 ≤p ≤ n1-Ɛ/2, and α(n) is the functional inverse of Ackermann's function which grows extremely slowly. The computational model we use in this paper is the EREW-PRAM. Our first algorithm, for the convex layers problem, belongs to EP, and the second one, for the envelope layers problem, belongs to the class EP if a small factor of log n is ignored.

Parallelizability of Some P-Complete Geometric Problems in the EREW-PRAM

A PRAM (Parallel Random Access Machine) [4] is the parallel computational model most notable for supporting the parallel algorithmic theory. It consists of a number of processors sharing a common memory. The processors communicate by exchanging data through a shared memory cell. Each processor can access any memory cell at one unit of time and all processors operate synchronously under the control of a common clock. These facts make the model a very advantageous platform for considering the inherent parallelism of problems. How ever, the development of parallel computers which fit this model has not quite matched the theoretical requests. The researches focusing on the reduction of this gap has been carried out [2, 5, 6, 7, 8, 9]. However, most of them give only theoretical analysis; the implementation of the PRAM on hardware level is seldom seen.

Carla Denise Castanho

Papers

Parallelizability of Some P-Complete Geometric Problems in the EREW-PRAM

A Hardware Implementation of PRAM and Its Performance Evaluation

Polynomially Fast Parallel Algorithms for Some P-Complete Problems

Polynomially fast parallel algorithms for some P-complete geometric problems

A Parallel Algorithm for Constructing Strongly Convex Superhulls of Points