A discrete cosine transform/inverse discrete cosine transform or DCT/IDCT integrated circuit capable of performing both DCT and IDCT, includes a processor for processing DCT/IDCT data including, input buffer and arithmetic logic unit for processing incoming data and first pass processed data, multiplier and accumulator unit for performing mathematical operations on DCT/IDCT data, and output buffer and arithmetic logic unit for processing first pass processed data and outgoing data. Also provided is an interleaved random access memory for storing DCT/IDCT data during various stages of processing.

Recycling dct/idct integrated circuit apparatus using a single multiplier/accumulator and a single random access memory

A picture encoding system which performs a prediction of picture element values within a block having a plurality of picture elements into which an original picture is divided, a discrete sine transform with respect to prediction error signals for obtaining a transform coefficient, a quantization of the transform coefficient for encoding quantized indexes, an inverse quantization of the quantized indexes for reproduction of the transform coefficient, an inverse discrete sine transform of the reproduced coefficient to reproduce the prediction error signal, and an addition thereto of the predicted picture element value for reproducing the picture element values within the block to employ them in predicting a next stage block to be encoded, whereby the block can be minimized in size while simplifying required transform operation.

Picture encoding system

In general, techniques are described for implementing an 8-point discrete cosine transform (DCT). An apparatus comprising an 8-point discrete cosine transform (DCT) hardware unit may implement these techniques to transform media data from a spatial domain to a frequency domain. The 8-point DCT hardware unit includes an even portion comprising factors A, B that are related to a first scaled factor (μ) in accordance with a first relationship. The 8-point DCT hardware unit also includes an odd portion comprising third, fourth, fifth and sixth internal factors (G, D, E, Z) that are related to a second scaled factor (η) in accordance with a second relationship. The first relationship relates the first scaled factor to the first and second internal factors. The second relationship relates the second scaled factor to the third internal factor and a fourth internal factor, as well as, the fifth internal factor and a sixth internal factor.

8-point transform for media data coding

This invention minimizes the number of non-trivial multiplications in the DCT process by rearranging the DCT process such that non-trivial multiplications are combined in a single process step. In particular, the DCT equations for the row-column application of the DCT process on k=pq points wherein p and q are relatively prime, are factored into a permutation matrix, a tensor product between matrices having p×p and q×q points, and a matrix whose product with an arbitrary vector having pq points requires pq-p-q+1 additions and/or subtractions. The tensor product is then further factored to remove non-trivial multiplications by developing a a first factor having (pq-p-q+1)/2 non-trivial multiplications and a diagonal matrix. The diagonal matrix is not unique for any set of data. Its j,j-th elements are chosen from a subproduct of the factorization of the tensor product. Once the diagonal matrix elements are chosen the remaining first factor is developed. When the factorization is complete, the diagonal matrix is absorbed into the quantization step which follows the DCT process. The quantization step is the multiplication of a diagonal matrix by the DCT output data. The quantization diagonal matrix is combined with the diagonal matrix of the DCT to form one multiplication process by which non-trivial elements multiply data. This combination of multiplication steps reduces the number of non-trivial multiplications in the DCT process.

Digital image processor for color image compression

A discrete cosine transforming apparatus for exercising a 2 n+1 th order discrete cosine transform includes a plurality of basic arithmetic circuits A including circuits for temporarily storing input data and adding the input data or subtracting the input data one from the other, and a plurality of another basic arithmetic circuits B including circuits for temporarily storing input data and adding the input data or subtracting the multiplication result data obtained by multiplying the sum or subtraction result by a multiplier that is equal to or less than the input data. The basic arithmetic circuit A is located at a first stage, and then the basic arithmetic circuit B and the arithmetic circuit A are alternately arranged, thereby to form a cascade connection of "n" stages. For the inverse transform, the same circuit arrangement as that for the cosine transform is used and the direction of a signal flow is inversed.

Discrete cosine transforming apparatus

A circuit for the fast calculation of the discrete cosine transform (X i ), 0≦i≦N-1, in which N=2 n and n is an integer of a signal defined by a sequence (x i ), 0≦i≦N-1 includes a first adder stage receiving the sequence (x i ), 0≦i≦N-1, and supplying two sequences (x i o ) and y i i ) and 0≦i≦(N/2)-1, a group of upper half-stages receiving the sequence of x o i ) and supplying the sequence (X 2q ) of the even components of the cosine transform. That group constitutes a circuit for the fast calculation of the cosine transform for a group of (N/2) points and a group of lower half-stages receiving the sequence (y i ) and supplying the sequence (X 2q+1 ) of the odd components of the cosine transform.

Cassimatis Eric

Papers

Circuit for the fast calculation of the direct or inverse cosine transform of a discrete signal

Quick computation calculation circuit for cosine conversion