A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digit redundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2 n. The computation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2. It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2 log2 n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Proposes two redundant CORDIC (coordinate rotation digital computer) methods with a constant scale factor for sine and cosine computation, called the double rotation method and the correcting rotation method. In both methods, the CORDIC is accelerated by the use of a redundant binary number representation, as in the previously proposed redundant CORDIC. In the proposed methods, since the number of rotation-extensions performed for each angle is a constant, the scale factor is a constant independent of the operand. Hence, one does not need to calculate the scale factor during the computation, and can make a more efficient sine and cosine generator than that based on the previous redundant CORDIC. >

Redundant CORDIC methods with a constant scale factor for sine and cosine computation

Signed-digit (SD) number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha , . . ., -1, 0, 1, . . ., alpha ), where alpha is an arbitrary integer in the range 1/2r >

Generalized signed-digit number systems: a unifying framework for redundant number representations

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54/spl times/54-bit multiplier is designed with this architecture. It is fabricated by 0.5 /spl mu/m CMOS with triple level metal technology. The active area size is 3.0/spl times/3.08 mm/sup 2/ and the number of transistors is 78,800. This is the smallest number for all 54/spl times/54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54/spl times/54-bit multipliers with 0.5-/spl mu/m CMOS.

An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture

Signed-digital number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha ,...,-1,0,1,..., alpha ), where alpha is an arbitrary integer in the range r/2 >

Carry-free addition of recoded binary signed-digit numbers

This paper investigates the logical design of a redundant binary adder with two input digits and one output digit, all in the digit set {1, 0, 1} Redundant binary arithmetic structures in which all digit sets are {1, 0, 1} were first discussed by Avizienis in 1961 Borovec studied the logical design of a class of such binary adders and subtracters in 1968 At that time, a variation of the adder/subtracter was overlooked This paper studies the logical design of this variation The sum digit is still a function only of the digits in three adjacent digital positions of the operands "Coupled don't cares" are encountered, but have not introduced too much difficulty The nine distinct formats (under permutation and negation) of representing three values with two bits given by Robertson are used The simplest adder/subtracter designs from this variation are less complex than the simplest designs previously known

Catherine Y. Chow

Papers

Logical design of a redundant binary adder