Cesar Galindo

TL;DR: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and the drain terminals of all other stages, is described in this paper.

TL;DR: An integrated circuit arrangement for providing erase voltages to a flash EEPROM memory array including one charge pump for generating a first high voltage with substantial current which may be used for application to the source terminals of flash memory cells during erase and to the gate terminals during programming was proposed in this paper.

TL;DR: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and the drain terminals of all other stages, is described in this paper.

TL;DR: An integrated circuit charge pump circuit including a plurality of stages, each stage including a first N type field effect switching transistor device having source and drain terminals connected in series with the source and the drain terminals of all other stages, is described in this paper.

TL;DR: An integrated circuit arrangement for providing erase voltage to a flash EEPROM memory array including one charge pump (32) for generating a first high voltage with substantial current which may be used for application to the source terminals of flash MEEMORY cells (34) during erase and to the gate terminals during programming, and another charge pump(33) for producing a second lower voltage as mentioned in this paper.