IEEE International Solid-State Circuits Conference

A Dual-Mode Sigma-Delta Modulator for GSM/WCDMA Receivers

Les convertisseurs analogique-numérique sigma-delta peuvent atteindre des résolutions très importantes (jusqu’à 24 bits) en contrepartie d’une bande passante utile inférieure au MHz. De telles résolutions peuvent être atteintes du fait du sur-échantillonnage ( oversampling) mis en œuvre dans ce type de convertisseur et de la mise en forme particulière du bruit de quantification ( noise shaping) qui tend à rejeter ce bruit hors de la bande utile (voir le calcul accompagnant la Figure°2 et l’illustration de la Figure 3).

Convertisseur sigma delta

An accurately tuned low-voltage linear continuous-time filter is presented in this paper. Accurate tuning is achieved using time-constant matched master-slave tuning combined with power-up mismatch calibration. A low-pass biquad designed for a corner frequency of 115 kHz achieves better than -80-dB total harmonic distortion with a 250-mVpp 10-kHz input signal. The prototype implemented in 0.18-μm CMOS process occupies an area of 0.4 mm 2 and dissipates 4.6 mW (2.6 mW for the filter and 2 mW for tuning) of power.

A 0.8-V accurately tuned linear continuous-time filter

Nowadays, communication devices are supporting an increasing number of standards. The diversity of the requirements in terms of speed and resolution, makes the design of a single low power analog to digital converter (ADC) suitable for all the scenarios very problematic. Reconfigurable ADCs are a solution to this problem, where resolution would be exchanged for bandwidth. Classical Delta Sigma ADCs offer an easy way to perform this exchange by adjusting their oversampling ratios. However, they are not suitable for wideband applications. Parallelizing Delta Sigma ADCs overcomes this problem and in addition, increases the reconfigurability of the ADC. In this work, a fully reconfigurable Time-interleaved Delta Sigma ADC is proposed. Its reconfigurability permits it to perform resolution-bandwidth trade-off as well as power consumptionbandwidth trade-off by adjusting the operation frequency, the number of active channels, the oversampling ratio and the modulator order. A novel interpolation technique is also proposed. It allows to downscale the capacitor sizes that may otherwise reach unreasonable values if large resolutions are required and relaxes the constraints on the anti-alias filter as well. A prototype of the presented Time-interleaved Delta Sigma ADC has been realized in a 1.2 V 65 nm CMOS technology. It was designed to fulfill the requirements of GSM, EDGE, UMTS, DVBT, WiFi and WiMax standards. For the GSM/EDGE scenario, a 80 dB SNR was measured. For the rest of scenarios, the performances were not secured but the functionality was tested successfully.

https://pastel.archives-ouvertes.fr/pastel-00609650/document

Chadi Jabbour

Papers

Conversion analogique numérique Sigma Delta reconfigurable à entrelacement temporel