A bus device is provided for use in a data processing system which includes a plurality of bus devices interconnected by a synchronous bus. The bus includes multiplexed data/address/arbitration lines which carry data, address, and arbitration information during respective data, command/address, and arbitration cycles. The bus also includes a BUSY line and a NO ARB line for controlling access to the data/address/arbitration lines. Where constructed as a memory device, the bus device includes memory circuits having a plurality of storage locations, and an interconnecting circuit which monitors the BUSY and NO ARB lines to identify various types of cycles on the bus, and which controls transmission of signals from the memory device over the bus in accordance with information derived by the monitoring means from the BUSY and NO ARB lines.

Bus device for use in a computer system having a synchronous bus

A node for obtaining access to a bus. In this arbitration method, the node receives a conditional grant. The node determines whether access to the bus will actually transfer to it. The node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When the node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Lookahead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers

A circuit breaker system uses a microprocessor for calculating at least one function of a measured current flow. The microprocessor provides other functions such as serial data stream communications, the ability of many circuit breaker systems to communicate with a central computer, storage of trip information concerning the last trip, storage of historical trip information concerning a number of past tips, EEPROM memory for storing trip information, the microprocessor may inhibit tripping on a high current fault to permit storage of trip information into a memory, power is derived from current transformers drawing energy from current flow to a load and the electronics are protected from high voltage caused by heavy current flow to the load, optical isolators are used for the circuit breaker to communicate with external equipment, a multi-turn resistor adjusts an external test voltage for testing the circuit breaker system, in the event that there is no load or a load drawing insufficient current to provide power for the electronics the circuit breaker may be externally powered to provide readout of electrically erasable programmable read only memory, the microprocessor reads setting switches and a multiplier plug. Also the microprocessor is capable of digitizing selected quantities frequently and of digitizing other quantities less frequently. A second microprocessor permits one microprocessor to sample voltage and current rapidly for metering purposes, and the second microprocessor operates other functions.

Computer-based metering arrangement including a circuit interrupter

A data transfer controller allows data to be transferred from a network bus to a system bus in a host computer. The controller has a network bus interface for communicating with the network bus and a system bus interface for communicating with the system bus. The system bus interface has first and second buffers. A dual port memory is utilized and has one port operatively connected to one of the buffers in the system bus interface and to a microprocessor. The direct access channel is established and operatively connected to the other buffer of the system bus interface as well as coupled to the microprocessor and associated control logic. A switch under control of the control logic establishes connections between the second port of the dual port memory and either the direct access channel or the network bus interface.

Multiple path multiplexed host to network data communication system

A secure front-end communication system which couples a plurality of actively redundant process control computers to a computer network. The system includes a front end computer which is capable of establishing time limited communication contracts with one or more computer entity on the computer network. Each time limited communication contract is based upon an acceptable response to the transmission of an unpredicable signal from the front end computer, such as an encrypted transformation of a psuedo-random number generated by the front end computer. A security table is used to identify the network entities that are permitted to send write command messages to the process control computers to which the front end computer is connected. The front end computer also includes at least one permissive table which is used to determined whether a write command message from the network entity should be transmitted to the process control computer for which the message was intended.

System and method for determining whether to transmit command to control computer by checking status of enable indicator associated with variable identified in the command

In a data processing system which uses a common bus for communication of address and data information among a plurality of system components, a bus timing technique uses a clock signal having a transfer time period which comprises a plurality of subperiods which requires address transfer to take place during a first selected group of subperiods and data to be transferred during a second selected group of subperiods with idle subperiods in between. A first control signal is generated by the data receiving or data supplying unit in order to inhibit access to the bus until such transfer is completed and a second control signal can be provided to lock-in bus access by such unit if desired for more than one transfer period. Appropriate priority is arranged for bus access among selected system components whether the common bus system has a single bus for use with a single port memory or a dual bus for use with a dual port memory.

Chandra R. Vora

Papers

Data processing system having unique bus control protocol