There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

コンピュータ・サイエンス : ACM computing surveys

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私の computer 環境

Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.

Methods for fault tolerance in networks-on-chip

Location estimation technology under the wireless environment has become a vital technology in the field of mobile edge computing. Especially, under the mobile edge of entire networks environment, indoor location estimation is gradually getting the interest research and application topic, due to technical constraints of global positioning system technology for indoor environment and the popularity of the mobile edge computing servers. In this paper, the widely used single-model framework for indoor localization is presented as an introduction, which consists of three stages: 1) sample data collection; 2) model building; and 3) localization estimation. And then, through analyzing of the actual scene of indoor localization, a new framework for indoor localization under mobile edge computing environment, named Multimodel, is proposed from the theoretical perspective. It is mainly based on the observation that the environment of the sample data collection and that of localization data collection may change seriously. In order to make up for the shortcomings of this framework, two combinatorial optimization problems are proposed. Later, we discuss the NP-hardness of them in several different cases. In addition, two heuristic algorithms are given, and the performance of which are illustrated by the corresponding experimental results.

Multimodel Framework for Indoor Localization Under Mobile Edge Computing Environment

Continuing decrease in the feature size of integrated circuits leads to increases in susceptibility to transient and permanent faults. This paper proposes a fault-tolerant solution for a bufferless network-on-chip, including an on-line fault-diagnosis mechanism to detect both transient and permanent faults, a hybrid automatic repeat request, and forward error correction link-level error control scheme to handle transient faults and a reinforcement-learning-based fault-tolerant deflection routing (FTDR) algorithm to tolerate permanent faults without deadlock and livelock. A hierarchical-routing-table-based algorithm (FTDR-H) is also presented to reduce the area overhead of the FTDR router. Synthesized results show that, compared with the FTDR router, the FTDR-H router can reduce the area by 27% in an 88 network. Simulation results demonstrate that under synthetic workloads, in the presence of permanent link faults, the throughput of an 8 8 network with FTDR and FTDR-H algorithms are 14% and 23% higher on average than that with the fault-on-neighbor (FoN) aware deflection routing algorithm and the cost-based deflection routing algorithm, respectively. Under real application workloads, the FTDR-H algorithm achieves 20% less hop counts on average than that of the FoN algorithm. For transient faults, the performance of the FTDR router can achieve graceful degradation even at a high fault rate. We also implement the fault-tolerant deflection router which can achieve 400 MHz in TSMC 65-nm technology.

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router

We propose a reconfigurable fault-tolerant deflection routing algorithm (FTDR) based on reinforcement learning for NoC. The algorithm reconfigures the routing table through a kind of reinforcement learning---Q-learning using 2-hop fault information. It is topology-agnostic and insensitive to the shape of the fault region. In order to reduce the routing table size, we also propose a hierarchical Q-learning based deflection routing algorithm (FTDR-H) with area reduction up to 27% for a switch in an 8 x 8 mesh compared to the original FTDR. Experimental results show that in the presence of faults, FTDR and FTDR-H are better than other fault-tolerant deflection routing algorithms and a turn model based fault-tolerant routing algorithm.

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip

Reliability has become a key issue of Networks-on-Chip (NoC) as the CMOS technology scales down to the nanoscale domain. This paper proposes a Fault-on-Neighbor (FoN) aware deflection routing algorithm for NoC which makes routing decision based on the link status of neighbor switches within 2 hops to avoid fault links and switches. Simulation results demonstrate that in the presence of faults, the saturated throughput of the FoN switch is 13% higher on average than a cost-based deflection switch for 8×8 mesh. The average hop counts can be up to 1.7× less than the cost-based switch. The FoN switch is also synthesized using 65nm TSMC technology and it can work at 500MHz with small area overhead.

Chaochao Feng

Papers

Methods for fault tolerance in networks-on-chip

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip

Mobile relay deployment in multihop relay networks