Showing papers by "Charles E. Leiserson published in 1983"

Optimizing synchronous systems

Abstract: Conception d'un algorithme efficace pour circuit integre a tres grande echelle. On presente une transformation convertissant les systemes synchrones en un systeme plus efficace et une implantation systolique en changeant les ondulations combinatoires. Le probleme pour l'optimisation du systeme peut etre reduit a un probleme de chemin le plus court a une seule destination

Optimizing Synchronous Circuitry by Retiming (Preliminary Version)

Abstract: This paper explores circuit optimization within a graph-theoretic framework. The vertices of the graph are combinational logic elements with assigned numerical propagation delays. The edges of the graph are interconnections between combinational logic elements. Each edge is given a weight equal to the number of clocked registers through which the interconnection passes. A distinguished vertex, called the host, represents the interface between the circuit and the external world.

Area-Efficient VLSI Computation

Abstract: The remarkable advance of very large scale integrated (VLSI) circuitry has sparked research into the design of algorithms suitable for direct hardware implementation. To exploit the massive parallelism offered by two-dimensional VLSI circuit technologies, the physical and logical structures of algorithms must be harmonized. A major goal is to design algorithms that are area-efficient as well as time-efficient, using complexity measures that reflect the true implementation costs. The two parts of this thesis address these two types of efficiency from a unified viewpoint of mathematics and engineering. Systolic systems make for high-performance hardware designs by marrying the ideas of pipelining and multiprocessing. A systolic system is a network of small, rhythmically computing processors which perform a service on behalf of a host computer. Despite their good performance characteristics, systolic systems can be hard to design because general global communication is prohibited. The first part of the thesis remedies this deficiency by providing a powerful methodology for designing systolic systems. It is shown that various kinds of global communication can be eliminated from a parallel system with virtually no performance penalty. In particular, if a systolic system has been augmented so that the host can broadcast to every processor in the system, the broadcasting can always be converted to local communication with almost no degradation in response time. Parallel systems can be designed with global communication and then converted to systolic systems, a methodology which is applied to the design of fast priority queues, counters, and pattern matchers. One of the designs is a device that dynamically shares its constituent processors among several fast priority queues so that no one queue overflows until the entire system overflows. In addition, it is shown that matrix computations--including matrix multiplication and LU-decomposition--can be performed by area-efficient systolic array algorithms. Having treated time-efficiency, the thesis next focuses on the question, "What interconnection structures have area-efficient layouts?" Good upper bounds for the area of layouts can be obtained for classes of graphs with good separator theorems. For example, any binary tree on n vertices has an O(n) area layout, and any bounded-degree planar graph has an O(nlg('2)n) area layout. The general algorithm that produces these layouts maintains a sparse representation for layouts that is based on the well-known UNION-FIND algorithm; as a result, the running time devoted to bookkeeping is nearly linear. Among the off-shoots of this work is an O(nlg('2)n) area chip which can implement an arbitrary tree of n vertices by making only n solder dot connections. Another result is a design for partitioning a complete binary tree into chips. Whereas the obvious packaging scheme requires two types of chips, one of which contains only a few nodes of the tree and has many off-chip connections, the new design requires only one type of chip which is packed full and has only four off-chip connections. The two parts of the thesis emphasize the contribution of communication to the performance and area of an integrated circuit. This concern complicates the classical model of parallel processing where communication is free and the measure of complexity is the number of operations. What is gained is a better understanding of integrated circuit computation in particular, and parallel computation in general. Combined, the two parts of the thesis provide mathematical views of an engineering discipline: techniques of theoretical computer science--e.g., divide and conquer, automata theory, asymptotic analysis--applied to integrated circuit computation.

Optimal Placement for River Routing

Abstract: River routing is the problem of connecting a set of terminals a 1,…,a n on a line to another set b 1,…,b n in order across a rectangular channel. When the terminals are located on modules, the modules must be placed relative to one another before routing. This placement problem arises frequently in design systems like bristle-blocks where stretch lines through a module can effectively break it into several chunks, each of which must be placed separately. This paper gives concise necessary and sufficient conditions for wirability which are applied to reduce the optimal placement problem to the graph-theoretic single-source-longest-paths problem. By exploiting the special structure of graphs that arise from the placement problem for rectilinear wiring, an optimal solution may be determined in linear time.

Systolic array apparatuses for matrix computations

Abstract: A systolic array system of inner product step processors is provided in the form of a mesh connected network which rhythmically compute and pass data through the system. Each processor in the system regularly feeds data in and out, each time performing some computation, so that a regular flow of data is kept up in the network. Many basic matrix computations can be readily and efficiently pipelined on systolic array network systems according to these inventions. Such arrays enjoy simple and regular communication paths and the individual processors in the networks are substantially all identical. Similar hexagonally connected processors can, for example, optionally perform matrix multiplication and LU-decomposition of a matrix. Linearly connected systolic arrays are useful for performing a variety of other computations.

Wafer-scale integration of systolic arrays

Abstract: This paper describes and analyzes several algorithms for constructing systolic array networks from cells on a silicon wafer. Some of the cells may be defective, and thus the networks must be configured to avoid them. We adopt a probabilistic model of cell failure, and attempt to construct networks whose maximum wire length is minimal Although the algorithms presented are designed principally for application to the wafer-scale integration of one and two-dimensional systolic arrays, they can also be used to construct networks in well studied models of geometric complexity. Some of the algorithms are of considerable practical interest.