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Showing papers by "Charles E. Leiserson published in 1984"


24 Feb 1984
TL;DR: The authors give a linear-area chip of m processors and only four off-chip connections which can be used as the sole building block to construct an arbitrarily large complete binary tree.
Abstract: : Many researchers have proposed that ensembles of processing elements be organized as trees. This paper explores how large tree machines can be assembled efficiently from smaller components. A principal constraint considered is the limited number of external connections from an integrated circuit chip. We also explore the emerging capability of restructurable VLSI which allows a chip to be customized after fabrication. The authors give a linear-area chip of m processors and only four off-chip connections which can be used as the sole building block to construct an arbitrarily large complete binary tree. They also present a restructurable linear-area layout of m processors with O(lg m) pins that can realize an arbitrary binary tree of any size. This layout is based on a solution to the graph-theoretic problem: Given a tree in which each vertex is either black or white, determine how many edges need be cut in order to bisect the tree into equal-size components, each containing exactly half the black and half of the white vertices. These ideas extend to more general graphs using separator theorems or bifurcators. (Author)

69 citations


Proceedings ArticleDOI
28 Nov 1984
TL;DR: A modification to the classical Gram-Schmidt algorithm which eliminates the use of division under certain assumptions is suggested and size and speed statistics are given for a projected .5 micron VHSIC implementation of the processor.
Abstract: The difficulties in designing systolic processors can be reduced by applying the architectural transformations of code motion, retiming, slowdown, coalescing, parallel/serial compromises and partitioning to a more easily designed combinational or semisystolic form of the processor. In this paper, the use of these transformations and the attendant tradeoffs in the design of architectures for adaptive filtering based on the Gram-Schmidt algorithm are considered. A modification to the classical Gram-Schmidt algorithm which eliminates the use of division under certain assumptions is suggested. Also, size and speed statistics are given for a projected .5 micron VHSIC implementation of the processor.© (1984) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

11 citations