Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.

Semiconductor processing system and methods using capacitively coupled plasma

An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Semiconductor processing systems having multiple plasma configurations

Embodiments of the invention provide a cluster tool configured to deposit a material onto a substrate surface by using one or more electroless, electrochemical plating, CVD and/or ALD processing chambers. In one aspect, a ruthenium-containing catalytic layer is formed. Embodiments of the invention provide a hybrid deposition system configured to deposit a seed layer on a substrate with an electroless process and to subsequently fill interconnect features on the substrate with an ECP cell. Other aspects provide an electroless deposition system configured to deposit a seed layer on a substrate, fill interconnect features on a substrate, or sequentially deposit both a seed layer and fill interconnect features on the substrate. One embodiment provides an electroless deposition system configured to form a capping layer over substrate interconnects. The system includes a vapor dryer for pre- and post-deposition cleaning of substrates as well as a brush box chamber for post-deposition cleaning.

Integrated electroless deposition system

An apparatus and a method of depositing a catalytic layer comprising at least one metal selected from the group consisting of noble metals, semi-noble metals, alloys thereof, and combinations thereof in sub-micron features formed on a substrate. Examples of noble metals include palladium and platinum. Examples of semi-noble metals include cobalt, nickel, and tungsten. The catalytic layer may be deposited by electroless deposition, electroplating, or chemical vapor deposition. In one embodiment, the catalytic layer may be deposited in the feature to act as a barrier layer to a subsequently deposited conductive material. In another embodiment, the catalytic layer may be deposited over a barrier layer. In yet another embodiment, the catalytic layer may be deposited over a seed layer deposited over the barrier layer to act as a “patch” of any discontinuities in the seed layer. Once the catalytic layer has been deposited, a conductive material, such as copper, may be deposited over the catalytic layer. In one embodiment, the conductive material is deposited over the catalytic layer by electroless deposition. In another embodiment, the conductive material is deposited over the catalytic layer by electroless deposition followed by electroplating or followed by chemical vapor deposition. In still another embodiment, the conductive material is deposited over the catalytic layer by electroplating or by chemical vapor deposition.

Electroless deposition apparatus

Embodiments of the invention generally provide methods of filling contact level features formed in a semiconductor device by depositing a barrier layer over the contact feature and then filing the layer using an PVD, CVD, ALD, electrochemical plating process (ECP) and/or electroless deposition processes. In one embodiment, the barrier layer has a catalytically active surface that will allow the electroless deposition of a metal on the barrier layer. In one aspect, the electrolessly deposited metal is copper or a copper alloy. In one aspect, the contact level feature is filled with a copper alloy by use of an electroless deposition process. In another aspect, a copper alloy is used to from a thin conductive copper layer that is used to subsequently fill features with a copper containing material by use of an ECP, PVD, CVD, and/or ALD deposition process. In one embodiment, a portion of the barrier layer is purposely allowed to react with traces of residual oxide at the silicon junction of the contact level feature to form a low resistance connection.

Contact metallization scheme using a barrier layer over a silicide layer

A solvent method for the metallization of a non-conductive surface with gold, nickel or copper is shown whereby on a substrate a thermosensitive coordination complex of palladium is deposited; the complex has the formula LmPdXn wherein L is a ligand or unsaturated organic radical, X is a halide, alkyl group or a bidentate ligand and m is an integer from 1 to 4 and n is from 0 to 3; trimethyl phosphite palladium dichloride complex is an appropriate illustration of the complex; the palladium complex is applied on the substrate in a suitable non-aqueous solution such as tetrahydrofuran solution; the complex is then baked in air at elevated temperature; the exposure to high temperature decomposes the complex leaving a residue which is catalytic to the deposition of gold, nickel, cobalt or copper from an electroless bath thereof; the non-conductive material is then immersed in an electroless bath to metallize the areas which have been rendered catalytic; the preferred thermosensitive coordination complex of palladium is trimethyl phosphite palladium dichloride; a requirement for a proper thermal exposure of the complex is that the substrate is capable of withstanding the elevated temperatures such as above 210°C; illustrative organic substrates are polyimides, polysulfones, silicones, vulcanizates, fluoroplastics, polyphenylene sulfides, polyparabanic acids, and polyhydantoin, etc.

Catalyst for electroless deposition of metals

An electric circuit has a flexible insulating carrier 2 with conductor tracks 4 on the surface. The conductor tracks consists of a deposited metal layer, each conductor track having been applied to a selectively sensitised area of the surface by currentless deposition of metal. The circuit is produced by printing a printing ink onto the surface along a line corresponding to the particular conductor. The printing ink is a polyester adhesive containing a palladium complex. The metal deposited currentless is on the complex.

Charles Roscoe Brummett

Papers

Catalyst for electroless deposition of metals

Printed circuit and printing ink for the conductor tracks thereof