C
Chau-Chin Huang
Researcher at National Taiwan University
Publications - 13
Citations - 265
Chau-Chin Huang is an academic researcher from National Taiwan University. The author has contributed to research in topics: Placement & Routing (electronic design automation). The author has an hindex of 9, co-authored 13 publications receiving 195 citations. Previous affiliations of Chau-Chin Huang include Synopsys.
Papers
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Journal ArticleDOI
NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs
Meng-Kai Hsu,Yi-Fang Chen,Chau-Chin Huang,Sheng Chou,Tzu-Hen Lin,Tung-Chieh Chen,Yao-Wen Chang +6 more
TL;DR: A novel design hierarchy identification technique to effectively identify design hierarchies and guide placement for better wirelength and routability and to further optimize routing congestion is presented.
Journal ArticleDOI
NTUplace4dr: A Detailed-Routing-Driven Placer for Mixed-Size Circuit Designs With Technology and Region Constraints
Chau-Chin Huang,Hsin-Ying Lee,Bo-Qiao Lin,Sheng-Wei Yang,Chin-Hao Chang,Szu-To Chen,Yao-Wen Chang,Tung-Chieh Chen,Ismail Bustany +8 more
TL;DR: This paper presents a high-quality placement algorithm to satisfy technology and region constraints and optimize DR routability with five major techniques: a clustering algorithm followed by two-round quadratic placement to obtain an initial placement satisfying region constraints.
Journal ArticleDOI
The Influence of Plastic Deformation and Cooling Rates on the Microstructural Constituents of an Ultra-low Carbon Bainitic Steel
TL;DR: In this paper, an experimental ultra-low carbon bainitic steel was prepared to investigate the effect of a prior compressive deformation on the morphology of the transformation procuct during continuous cooling.
Proceedings ArticleDOI
Routability-driven placement for hierarchical mixed-size circuit designs
TL;DR: A novel two-stage technique to effectively identify design hierarchies and guide placement for better wirelength and routability and a new analytical net-congestion-optimization technique is proposed.
Journal ArticleDOI
Clock-aware placement for large-scale heterogeneous FPGAs
TL;DR: A novel clock-aware placement algorithm for large-scale heterogeneous FPGAs that achieves the best overall routed wirelength and outperforms the top-3 winners based on the 2017 ISPD Clock-Aware Placement Contest benchmark suite.