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Author

Yao-Wen Chang

Bio: Yao-Wen Chang is an academic researcher from National Taiwan University. The author has contributed to research in topic(s): Routing (electronic design automation) & Equal-cost multi-path routing. The author has an hindex of 45, co-authored 382 publication(s) receiving 8378 citation(s). Previous affiliations of Yao-Wen Chang include MediaTek & National Chiao Tung University.
Papers
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Proceedings ArticleDOI
Yu-Jie Cai1, Yang Hsu1, Yao-Wen Chang1Institutions (1)
05 Dec 2021
Abstract: In modern packaging technology, redistribution layers (RDLs) are often used to redistribute interconnections among multiple chips and between I/O pads and bump pads. For high-density RDL routing, irregular vias, where vias can be placed at arbitrary locations, are adopted to better utilize RDL resources to obtain desired routing solutions. As the problem size increases, however, using irregular vias may suffer from high computation overheads. Moreover, most previous works route pre-assignment (PA) and free-assignment (FA) nets in separate stages, incurring routing resource competition. To remedy these disadvantages, we propose a simultaneous PA and FA routing framework with irregular RDL via planning. In this paper, we first propose a novel partitioning method based on the Voronoi diagram to handle irregular via structures and derive a theoretical upper bound on the number of generated regions. We then propose a chord-based tile model and a net-sequence list to generate non-crossing guides for PA and FA nets on the same routing graph. Finally, we develop a novel geometry-based pattern routing to obtain the final solutions. Experimental results show that our work can achieve 100% routability and an average 30X speedup over the-state-of-the-art work.

Proceedings ArticleDOI
05 Dec 2021
Abstract: The topological quantum error correction (TQEC) scheme is promising for scalable and reliable quantum computing. A TQEC circuit can be modeled by a three-dimensional diagram, and the implementation resource of a TQEC circuit is abstracted to its space-time volume. Implementing a quantum algorithm with a reasonable physical qubit number and reasonable computation time is challenging for large-scale practical problems. Therefore, minimizing the space-time volume of a TQEC circuit becomes a crucial issue. Previous work shows that bridge compression can greatly compress TQEC circuits, but it was performed only manually. It is desirable to develop automated compression techniques for TQEC circuits to achieve low-overhead, large-scale quantum computations. In this paper, we present the first work that can automatically perform bridge compression on TQEC circuits. Compared with the state-of-the-art method, experimental results show that our proposed algorithm can averagely reduce space-time volumes by 83%.

Proceedings ArticleDOI
05 Dec 2021
Abstract: AI-dedicated hardware designs are growing dramatically for various AI applications. These designs often contain highly connected circuit structures, reflecting the complicated structure in neural networks, such as convolutional layers and fully-connected layers. As a result, such dense interconnections incur severe congestion problems in physical design that cannot be solved by conventional placement methods. This paper proposes a novel placement framework for CNN accelerator units, which extracts kernels from the circuit and insert kernel-based regions to guide placement and minimize routing congestion. Experimental results show that our framework effectively reduces global routing congestion without wirelength degradation, significantly outperforming leading commercial tools.

Proceedings ArticleDOI
Ming-Hung Chen1, Yao-Wen Chang1, Jun-Jie Wang1Institutions (1)
05 Dec 2021
Abstract: A multi-FPGA system consists of multiple FPGAs connected by physical wires, and a circuit is partitioned to fit each FPGA and routed on the system by such physical wires. Due to the limited numbers of input/output (I/O) pins in an FPGA, however, not all signals can be transmitted between FPGAs directly. Moreover, the routing resource may not be sufficient to accommodate many cross-FPGA signals from circuit partitioning. As a result, input/output time-division multiplexing (TDM) is introduced to send a group of cross-FPGA signals in a routing channel with a timing penalty. To optimize the performance of such a system, we shall develop a simultaneous partitioning and routing algorithm considering the timing penalty caused by I/O TDM. Considering the TDM delay penalty, we propose a simultaneous partitioning and routing algorithm to remedy the insufficiency of the two-stage flow of partitioning followed by routing. Our algorithm consists of two major steps: (1) a novel routing-aware partitioning framework to obtain an initial solution considering irregular, asymmetric connections, and (2) a partition-aware routing scheme to optimize routing in each partitioning pass. Experimental results show that our proposed algorithm can achieve better timing than the classical flow.

Proceedings ArticleDOI
Bingshu Wang1, Lanfan Jiang1, Wenxing Zhu1, Longkun Guo1  +2 moreInstitutions (3)
05 Dec 2021
Abstract: The data imbalance problem often occurs in nanometer VLSI applications, where normal cases far outnumber error ones. Many imbalanced data handling methods have been proposed, such as oversampling minority class samples and downsampling majority class samples. However, existing methods focus on improving the quality of minority classes while causing quality deterioration of majority ones. In this paper, we propose a two-stage classifier to handle the data imbalance problem. We first develop an iterative neural network framework to reduce false alarms. Then the oversampling method on a final classification network is applied to predict the two classes better. As a result, the data imbalance problem is well handled, and the quality deterioration of majority classes is also reduced. Since the iterative stage does not change any existing network structure, any convolutional neural network can be used in the framework. Compared with the state-of-the-art imbalanced data handling methods, experimental results on the hotspot detection problem show that our two-stage classification method achieves the best prediction accuracy and reduces false alarms significantly.

Cited by
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Journal ArticleDOI
ZhuLingjun1, ChaudhuriArjun2, BanerjeeSanmitra2, MuraliGauthaman1  +3 moreInstitutions (2)
Abstract: Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and ...

Book ChapterDOI
01 Jan 2022
Abstract: In complementary metal–oxide–semiconductor (CMOS) logic circuits, the main design requirement for low-power applications is to reduce the power dissipation. Dynamic power dissipation occurs in clock network which contributes up to 30–45% of total power dissipation of circuit mostly because of flip-flop are being used for sequencing which consumes lot of power therefore to reduce the power consumption flip-flop are being replaced with pulsed latch circuit with feedback. Conditional circuit is used in bidirectional shift register with bidirectional pulsed latch circuit. When it is compared with master–slave flip-flop, power reduction is 38%. Modified circuit is being implemented in 28 nm CMOS technology.


Journal ArticleDOI
Nafiseh Masoudi1, Georges M. Fadel1Institutions (1)
TL;DR: A computationally efficient approach is proposed to optimize the layout of flexible connectors (e.g., cable harnesses) by minimizing their overall length while maximizing their common length.
Abstract: The components of complex systems such as automobiles or ships communicate via connectors, including wires, hoses, or pipes whose weight could substantially increase the total weight of the system. Hence, it is of paramount importance to lay out these connectors such that their overall weight is minimized. In this paper, a computationally efficient approach is proposed to optimize the layout of flexible connectors (e.g., cable harnesses) by minimizing their overall length while maximizing their common length. The approach provides a framework to mathematically model the cable harness layout optimization problem. A Multiobjective Genetic Algorithm (MOGA) solver is then applied to solve the optimization problem, which outputs a set of non-dominated solutions to the bi-objective problem. Finally, the effects of the workspace’s geometric structure on the optimal layouts of cable harnesses are discussed using sample test cases. The overarching objective of this study is to provide insight for designers of cable harnesses when deciding on the final layout of connectors considering aspects such as accessibility to and maintainability of these connectors.

1 citations


Proceedings ArticleDOI
Yu-Jie Cai1, Yang Hsu1, Yao-Wen Chang1Institutions (1)
05 Dec 2021
Abstract: In modern packaging technology, redistribution layers (RDLs) are often used to redistribute interconnections among multiple chips and between I/O pads and bump pads. For high-density RDL routing, irregular vias, where vias can be placed at arbitrary locations, are adopted to better utilize RDL resources to obtain desired routing solutions. As the problem size increases, however, using irregular vias may suffer from high computation overheads. Moreover, most previous works route pre-assignment (PA) and free-assignment (FA) nets in separate stages, incurring routing resource competition. To remedy these disadvantages, we propose a simultaneous PA and FA routing framework with irregular RDL via planning. In this paper, we first propose a novel partitioning method based on the Voronoi diagram to handle irregular via structures and derive a theoretical upper bound on the number of generated regions. We then propose a chord-based tile model and a net-sequence list to generate non-crossing guides for PA and FA nets on the same routing graph. Finally, we develop a novel geometry-based pattern routing to obtain the final solutions. Experimental results show that our work can achieve 100% routability and an average 30X speedup over the-state-of-the-art work.

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Performance
Metrics

Author's H-index: 45

No. of papers from the Author in previous years
YearPapers
20219
202010
201910
201813
201717
201617