A novel approach for minimizing power during scan testing is presented. The idea is that given a full scan module or core that has multiple scan chains, the test set is generated and ordered in such a way that some of the scan chains can have their clock disabled for portions of the test set. Disabling the clock prevents flip-flops from transitioning, and hence reduces switching activity in the circuit. Moreover, disabling the clock also reduces power dissipation in the clock tree which often is a major source of power. The only hardware modification that is required to implement this approach is to add the capability for the tester to gate the clock for one subset of the scan chains in the core. A procedure for generating and ordering the test set to maximize the we of scan disable is described. Experimental results are shown indicating that the proposed approach can significantly reduce both logic and clock power during testing.

Reducing power dissipation during test using scan chain disable

This paper proposes a new approach to multi-level logic optimization based on ATPG (Automatic Test Pattern Generation). Previous ATPG-based methods for logic minimization suffered from the limitation that they were quite restricted in the set of possible circuit transformations. We show that the ATPG-based method presented here allows (in principle) the transformation of a given combinational network C into an arbitrary, structurally different but functionally equivalent combinational network C'. Furthermore, powerful heuristics are presented in order to decide what network manipulations are promising for minimizing the circuit. By identifying indirect implications between signals in the circuit, transformations can be derived which are “good” candidates for the minimization of the circuit. In particular, it is shown that Recursive Learning can derive “good” Boolean divisors justifying the effort to attempt a Boolean division. For 9 out of 10 ISCAS-85 benchmark circuits our tool HANNIBAL obtains smaller circuits than the well-known synthesis system SIS.

http://www.cecs.uci.edu/~papers/compendium94-03/papers/1994/iccad94/pdffiles/01a_2.pdf

Multi-level logic optimization by implication analysis

A fast fault simulation approach based on ordinary logic emulation is proposed. The circuit configured into our system that emulates the faulty circuit's behaviour is synthesized from the good circuit and the given fault list in a novel way. Fault injection is made easy by shifting the content of a fault injection scan chain or by selecting the output of a parallel fault injection selector, with which we get rid of the time-consuming bit-stream regeneration process. Experimental results for ISCAS-89 benchmark circuits show that our serial fault emulator is about 20 times faster than HOPE. The speedup grows with the circuit size by our analysis. Two hybrid fault emulation approaches are also proposed. The first reduces the number of faults actually emulated by screening off faults not activated or with short propagation distances before emulation, and by collapsing nonstem faults into their equivalent stem faults. The second reduces the hardware requirement of the fault emulator by incorporating an ordinary fault simulator.

Sequential circuit fault simulation using logic emulation

We propose a static compaction procedure to reduce the test application time for full and partial scan synchronous sequential circuits. The procedure accepts as input a set of test subsequences. For every subsequence, it also accepts the vector to be scanned-in before the subsequence is applied. The procedure uses two operations to reduce the test application time. The first operation combines test subsequences. The second operation reduces the lengths of the combined subsequences. The reductions in test application time of the proposed procedure are demonstrated through experimental results.

Static test compaction for scan-based designs to reduce test application time

This paper presents a new testing method for sequential circuits, called reduced scan shift, which generates short test sequences In this method, only part of flip-flops close to the scan input line are controlled and another part of flip-flops close to the scan output line are observed by scan shift operations as small as possible For the purpose of reducing scan shift operations, the following points are considered: (1) how to decide target faults which each test vector should detects, (2) how to arrange flip-flops in the scan chain, (3) how to decide the order of test vectors Experimental results for ISCAS'89 benchmark circuits are given to show the effectiveness of this method

Reduced scan shift: a new testing method for sequential circuits

The reduction of test application time for the general scan designed circuits has been studied. The reduction problem is investigated from three aspects: the test generation, selective scans, and rearrangement of scan path. The two phase testing strategy has been proposed to employ scan only for the hard-to-detect faults. Four cases of selective scan have also been identified. Furthermore, an ordering heuristic without layout constraint has been proposed to maximize the reduction of unnecessary scans and hence the test application time. Applying these reduction methods, the total test clock-cycles can be reduced to only 20% on average for ISCAS sequential benchmark circuits with partial scan. >

Test time reduction in scan designed circuits

A novel parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm partitions a given test sequence into subsequences of equal length and then performs fault simulation with these subsequences in parallel. To overcome the state dependency of sequential circuits, a multiple-pass method is developed to use minimal simulation passes. The experimental results of PSF on the benchmark circuits show that the speedup ratio over a serial sequence fault simulator is 6.6 on average for random test sequences. >

Parallel sequence fault simulation for synchronous sequential circuits

A parallel sequence fault simulation (PSF) algorithm for synchronous sequential circuits is presented. The algorithm divides a given test sequence into subsequences of equal length and then performs multiple-pass fault simulation with these subsequences in parallel. The experimental results on the benchmark circuits show that the speedup ratio over a differential serial fault simulator is 4.90 on average for random test sequences. Conceptually, the PSF is an extension of the parallel pattern single fault propagation (PPSFP) and it reduces to PPSFP for combinational circuits. >

Chen-Pin Kung

Papers

Test time reduction in scan designed circuits

Parallel sequence fault simulation for synchronous sequential circuits

Parallel sequence fault simulation for synchronous sequential circuits