Showing papers by "Chen-Yi Lee published in 1994"

High-throughput data compressor designs using content addressable memory

Abstract: This paper presents a novel VLSI architecture for high-speed data compressor designs which implement the well-known LZ77 algorithm. The architecture mainly consists of three units, namely content addressable memory, match logic, and output stage. The content address memory generates a set of hit signals which identify those positions whose symbols in a specified window are the same as input symbol. These hits signals are then passed to the match logic which determines one matched stream and its match length and location in the window to form the kernel of compressed data. These two items are then passed to the output stage for packetization before sent out. By trading off hardware complexity and compression ratio, 2KB window size and adjustable maximum match length are considered in our proto-type VLSI chip. Simulation results show that, based on a 0.8 /spl mu/m CMOS process technology, clock speed up to 50 MHz can be achieved. This implies that the developing data compressor chip can handle many real-life applications such as in video coding and high-speed data storage systems. >

A parallel bit-level maximum/minimum selector for digital and video signal processing

Abstract: This paper presents a novel circuit for parallel bit-level maximum/minimum selection. The selection is based on a label-updating scheme which sequentially scans a set of data patterns from MSB to LSB and generates corresponding labels. The complete circuit realizing this scheme consists of a set of updating units and a global OR unit, where each updating unit is composed of only a few basic gates. Due to structure modularity, the developed circuit provides a very cost-effective hardware solution for comparing large volumes of data patterns as those required in digital and video signal processing. >

Design of a fast sequential decoding algorithm based on dynamic searching strategy

Abstract: This paper presents a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both sorting and path recording techniques. By means of sorting we can identify the correct path in a very fast way and then, by path recording, we can recover the bit sequence without degrading decoding performance. We also develop a conditional resetting scheme to overcome the buffer overflow problem encountered in conventional sequential decoding algorithms. Simulation results show that for a given code, decoding efficiency remains the same as that obtained from maximum likelihood function by appropriately selecting sorting length and decoding depth. In addition, this algorithm can be mapped onto an area-efficient VLSI architecture to implement long constraint length convolutional decoders for high-speed digital communications. >

Finite state vector quantization with multi-path tree search strategy for image/video coding

Abstract: This paper presents a new vector quantization (VQ) algorithm exploiting the features of tree-search as well as finite state VQs for image/video coding. In the tree-search VQ, multiple candidates are identified for on-going search to optimally determine an index of the minimum distortion. In addition, the desired codebook has been reorganized hierarchically to meet the concept of multi-path search of neighboring trees so that picture quality can be improved by 4 dB on the average. In the finite state VQ, adaptation to the state codebooks is added to enhance the hit-ratio of the index produced by the tree-search VQ and hence to further reduce compressed bits. An identifier code is then included to indicate to which output indices belong. Our proposed algorithm not only reaches a higher compression ratio but also achieves better quality compared to conventional finite-state and tree-search VQs. >