A multilayer wiring substrate wherein a substrate of ceramic material (11) contains a plurality of power supply wiring layers (1) and is formed with first and second through-holes (20,20a) Each of the first through-holes (20) contains a first metal layer (32,33) which is connected to at least one of the power supply wiring layers (12,13) Each of the second through-holes (20a) has a wall surface coated with a layer of a fluoride resin dielectric (21) with a second metal layer (22) formed on the coating A circuit is supplied with power via the first metal layers and with signals via the second metal layers The circuit comprises thin film wiring layers (25) formed on the substrate, insulating layers (24) made of an organic material, and electronic circuit elements (not shown) The substrate is made by coating upper and lower surfaces and through-holes of a substrate with a layer of the fluid resin dielectric, removing the coating from the upper and lower surfaces, forming a metal layer in the upper and lower surfaces and on the coating and removing the metal layer except for portions at each end of and within the through-holes

Multilayer wiring substrate

A three-layer BGA package includes a BGA Vss plane disposed between upper and lower BGA package traces, and also includes upper and lower BGA package Vss traces on the outer periphery of the BGA package. Vias electrically and thermally couple the BGA Vss plane to upper and lower BGA package Vss traces. Other vias electrically couple Vdd and IC signals from Vdd and signal traces on the upper and lower surfaces of the BGA package. Solder balls connected to the BGA package lower traces are soldered to matching traces on a system PCB. The periphery Vss traces, vias and solder balls help maintain current flow in the BGA Vss plane. In addition to providing a low impedance current return path (and thus reduced ground bounce and reduced IC signal delay time) for current sunk by an IC within the BGA package, the BGA Vss plane provides heat sinking. A four-layer BGA package further includes a BGA Vdd plane located intermediate the BGA Vss plane and the traces on the lower surface of the BGA package. Fabricated from two pieces of symmetrical printed circuit board material, this embodiment reduces ground bounce for IC current sourcing as well as IC current sinking, and provides approximately a 100% improvement in thermal dissipation as compared to prior art BGA packages.

Ball grid array package for a integrated circuit

A multilayered integrated circuit chip carrier has a top layer, a signal line layer, a ground layer, a power conductor layer, and a bottom layer with a separating layer between adjacent layers. Each layer has coplanar conductive and dielectric portions, the separating layers being primarily dielectric. The top layer supports an integrated circuit chip and signal launcher pads on the bottom layer couple signal and power lines of a printed circuit board to spaced points about the bottom layer periphery and substantially constant signal line impedance is achieved. The signal line layer is separated from the power conductor layer by a ground plane layer. Conductive via through pads are placed in the separating layers to form a plurality of separate conductive paths from each of the bottom and top layers to each of the signal line and power conductor layers. Via through pads are also placed in the separating layers to break up cavities and thus increase cavity resonance above signal frequencies and are placed in the signal line layer to provide signal line isolation. Thermal columns of via pads in the separating layers and conductive portions in the other layers under the chip provide chip cooling. Large grounded conductive areas in the top and bottom layers reduce unwanted signal coupling to the external environment. A capacitive coupling on the top layer between a power conductor and ground provides power line isolation.

Microwave multiport multilayered integrated circuit chip carrier

A high-speed, high pin-out chip carrier package (10) for interconnecting at least one LSI or VLSI chip to a circuit pack is disclosed. The package includes a ground plane (19), a power plane (20), and at least one signal layer (15, 16, 17, 18) containing plural conductors therethrough. Layers (85) of dielectric material separate adjacent conductive layers, (15, 16, 17, 18, 19, 20). By controlling, in design, the width of each signal conductor and its distance to the nearest ground (19) or power plane (20), the package is impedance-matched to the circuit pack. Plural plated-through holes (21) are disposed through the package for electrically interconnecting the signal conductors, the ground plane (19), and the power plane (20) to the circuit pack, and are arranged in a pattern to reduce inductive noise.

High-speed, high pin-out LSI chip package

An enclosure for electronic systems provides substantially total RF isolation of separate segments of a system except for the transmission of desired signals between different segments, even though the various segments are fabricated on a common circuit board. A special multilayer circuit board configuration makes this isolation feasible. Buffer circuits connected to drive signals on and receive signals from conductors which extend between isolated compartments prevent communication of stray signals along those conductors.

RF signal shielding enclosure of electronic systems

Multilayer printed circuit for signals whose rise time is less than one nanosecond. The conductive layers are stacked in the following order starting at any of the outer faces: connecting layer, ground layer, supply layer, ground layer. Thus, connections may be made by means of fixed-impedance microstrip lines and supply by means of very low impedance strip lines (less than a fraction of 1 ohm).

Cherdo Claude

Papers

Multilayer printed circuit

Mehrschichtige gedruckte Schaltung