A method and apparatus for transmitting/receiving control information in a wireless communication system are provided, in which physical layer signaling information to be transmitted in a frame is determined, a coded block is generated from signaling information having a fixed number of bits included in the physical layer signaling information, and a frame including the coded block is transmitted. The signaling information having the fixed number of bits includes information required for receiving other signaling information having a variable number of bits.

Method and apparatus for transmitting/receiving control information in a wireless communication system

The invention discloses a convolutional interleaving method and device. The method comprises the following steps of: initializing an address offset of each branch of convolutional interleaving in a SDRAM(Synchronous Dynamic Random Access Memory) to be B-1; while performing the convolutional interleaving, adding an initial address of each branch of the convolutional interleaving and a current address offset of the branch together to obtain an actual access address of data of the branch in the SDRAM; when the address offset of the ith branch of convolutional interleaving in the SDRAM is equal to (i-1)*M, resetting the address offset of the ith branch to be B-1, wherein B is the total number of the branches of the convolutional interleaving, i is a positive integer not less than 2 and not more than B, and M is interleaving depth of the convolutional interleaving. The method realizes shorter address hop among the branches in the convolutional interleaving process, greatly reduces trans-regional hop of addresses while accessing data in the SDRAM, and then realizes high-efficiency time domain convolutional interleaving, so that a clock period for processing one superframe is reduced obviously; and in comparison with the existing design, the method may improve a throughput rate by 64%.

Convolutional interleaving method and convolutional interleaver

Systems and methodologies are described that facilitate automatically generating interleaved addresses based on quadratic permution polynomials (QPP) during turbo decoding. An efficient recursive technique can be employed in which layers of nested loops enable the computation of a polynomial f(x) = (ax + bx2) mod N and a modular function given interleaved parameters "a" and "b" from a look up table. With the recursive technique, interleaved addresses can be generated, one interleaved address per clock cycle which can maintain turbo decoding performance.

Recursive realization of polynomial permutation interleaving

Convolutional de-interleaver

A convolutional interleaving and de-interleaving circuit and the method thereof are provided. The convolutional interleaving and de-interleaving circuit includes an initial address generator, a first address generator, a second address generator, an address mixer, an adder, a controller and a memory. Wherein, the controller enables those address generators to provide or store corresponding channel addresses. Further, an adder is shared and memory addresses are appropriately arranged so as to reduce the requirement of registers. Accordingly, the required gate count and the chip layout area can be reduced.

Convolutional interleaving and de-interleaving circuit and method thereof

A convolutional interleaving and de-interleaving circuit and method are disclosed. The convolutional interleaving and de-interleaving circuit comprises an initial address generator, a first address generator, a second address generator, an address mixer, an adder, a controller and a memory. Wherein the controller enables those address generators to be provided or stored in the corresponding channel addresses, and an adder commonly used is utilized. Arranging appropriately memory addresses can reduce the requirement of registers. Then, the decrease of the required gate count and the chip layout area can be easily achieved.

Chia-Chun Lin

Papers

Convolutional interleaving and de-interleaving circuit and method thereof

Convolutional interleaving and de-interleaving circuit and method