A general model is introduced which is capable of making accurate, quantitative predictions about the phase noise of different types of electrical oscillators by acknowledging the true periodically time-varying nature of all oscillators. This new approach also elucidates several previously unknown design criteria for reducing close-in phase noise by identifying the mechanisms by which intrinsic device noise and external noise sources contribute to the total phase noise. In particular, it explains the details of how 1/f noise in a device upconverts into close-in phase noise and identifies methods to suppress this upconversion. The theory also naturally accommodates cyclostationary noise sources, leading to additional important design insights. The model reduces to previously available phase noise models as special cases. Excellent agreement among theory, simulations, and measurements is observed.

/pdf/a-general-theory-of-phase-noise-in-electrical-oscillators-a928ervz6d.pdf

A general theory of phase noise in electrical oscillators

We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

The various arguments for introducing optical interconnections to silicon CMOS chips are summarized, and the challenges for optical, optoelectronic, and integration technologies are discussed. Optics could solve many physical problems of interconnects, including precise clock distribution, system synchronization (allowing larger synchronous zones, both on-chip and between chips), bandwidth and density of long interconnections, and reduction of power dissipation. Optics may relieve a broad range of design problems, such as crosstalk, voltage isolation, wave reflection, impedence matching, and pin inductance. It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures. No physical breakthrough is required to implement dense optical interconnects to silicon chips, though substantial technological work remains. Cost is a significant barrier to practical introduction, though revolutionary approaches exist that might achieve economies of scale. An Appendix analyzes scaling of on-chop global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.

/pdf/rationale-and-challenges-for-optical-interconnects-to-5clh2238g9.pdf

Rationale and challenges for optical interconnects to electronic chips

A geometric program (GP) is a type of mathematical optimization problem characterized by objective and constraint functions that have a special form. Recently developed solution methods can solve even large-scale GPs extremely efficiently and reliably; at the same time a number of practical problems, particularly in circuit design, have been found to be equivalent to (or well approximated by) GPs. Putting these two together, we get effective solutions for the practical problems. The basic approach in GP modeling is to attempt to express a practical problem, such as an engineering analysis or design problem, in GP format. In the best case, this formulation is exact; when this is not possible, we settle for an approximate formulation. This tutorial paper collects together in one place the basic background material needed to do GP modeling. We start with the basic definitions and facts, and some methods used to transform problems into GP format. We show how to recognize functions and problems compatible with GP, and how to approximate functions or data in a form compatible with GP (when this is possible). We give some simple and representative examples, and also describe some common extensions of GP, along with methods for solving (or approximately solving) them.

/pdf/a-tutorial-on-geometric-programming-47sdznbzxw.pdf

A tutorial on geometric programming

A companion analysis of clock jitter and phase noise of single-ended and differential ring oscillators is presented. The impulse sensitivity functions are used to derive expressions for the jitter and phase noise of ring oscillators. The effect of the number of stages, power dissipation, frequency of oscillation, and short-channel effects on the jitter and phase noise of ring oscillators is analyzed. Jitter and phase noise due to substrate and supply noise is discussed, and the effect of symmetry on the upconversion of 1/f noise is demonstrated. Several new design insights are given for low jitter/phase-noise design. Good agreement between theory and measurements is observed.

/pdf/jitter-and-phase-noise-in-ring-oscillators-qgelzm28bv.pdf

Jitter and phase noise in ring oscillators

Multipath ring oscillators have been used to generate multiple clock phases and higher oscillation frequencies. This paper presents a modified linear analysis to find an accurate ex- pression for the oscillationfrequency and phase noise. The analysis shows that for the same power consumption, the number of phases can be increased without decreasing the oscillation frequency or degrading the phase noise. The expression further indicates factors that determine the oscillation frequency and shows that in principle, the maximum oscillation frequency can exceed that of a three-stage ring oscillator. The analytical results can be used to find the optimum coupling structure of the oscillator to achieve a desired operating frequency and phase noise performance.

https://ieeexplore.ieee.org/iel5/8919/6029391/05767529.pdf

Design and Optimization of Multipath

A two-stage hybrid power management unit (PMU) is presented with a highly-efficient novel ON-OFF LDO as the second stage. The proposed design targets IoT sensor nodes that require sub-microwatt power levels with regulated supply voltages. The first stage provides the initial step-down using a switched-capacitor based DC-DC converter with the power efficiency of >97% at sub-microwatt levels. The output voltage from the first stage is then regulated using the proposed ON-OFF LDO. The LDO can regulate the output voltage with a dropout voltage of <30mV. To minimize quiescent power loss, the LDO control structure is all digital and consumes no static current. The hybrid structure achieves an aggregate peak power efficiency of 85% at a load of 0.8µW with low ripples <10mV. The control circuitry for both stages consumes static current <60nA. The design is implemented in 28-nm CMOS and occupies an active area of 0.0043mm2.

An 85%-Efficiency Hybrid DC-DC Converter for Sub-Microwatt IoT Applications

This paper presents a fully integrated CMOS LC oscillator with digital tuning. The frequency tuning is by averaging over two oscillation frequencies. The average frequency is determined by the digital input pattern, which switches a small unit of capacitance on and off the main capacitor. Measurements in a 0.18 /spl mu/m CMOS test-chip shows that 5 bits of additional resolution can be achieved. With the inductor dominating the quality factor, Q, the phase noise remains almost the same, not affected by this averaging activity.

CMOS LC oscillator using variable mean frequency

An 86.6-dB SFDR, 1-GS/s differential bootstrap sampler in a 0.18-um SiGe BiCMOS technology is presented. The performance is achieved using an amplitude-modulated bootstrap circuit. The results show 14-bit linearity over nearly 500-MHz bandwidth, while consuming less power compared to a conventional MOSFET switched-capacitor bootstrap circuit due to less parasitic capacitance and the use of high ft HBT.

A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input

A100 GHz wideband static divider is implemented on a 0. 1S$\mu$mSiGe BiCMOS technology. The divider achieves a self-resonant frequency (SRF) of 92.5 GHz with a maximum dividing frequency of 100 GHz. The required input power is less than 0dBm across the entire operating range. The divider consumes 66 mW. The circuit has a 100 x SO $\mu \mathrm{m}^{2}$ active area

Chih-Kong Ken Yang

Papers

Design and Optimization of Multipath

An 85%-Efficiency Hybrid DC-DC Converter for Sub-Microwatt IoT Applications

CMOS LC oscillator using variable mean frequency

A 14-bit 1-GS/s SiGe Bootstrap Sampler for High Resolution ADC with 250-MHz Input

A Low Power 100 GHz Static CML Frequency Divider in 0.18 μm SiGe BiCMOS Technology