An uninterruptible power supply (UPS) system includes an AC power input configured to receive AC power from a single-phase AC power source or a multi-phase AC power source, a DC power source, an output circuit including a power output, a controllable switch configured to selectively couple at least one of the AC power input and the DC power source to the output circuit, and a processor coupled and configured to affect operation of the output circuit depending upon which of single-phase and multi-phase operation of the UPS is indicated.

Uninterruptible power supply

A power factor correcting power supply includes an input stage power converter and an output stage power converter. The input stage power converter includes a plurality of series connected boost switches and a power factor correction controller. The power factor correction controller may direct the operation of the boost switches with series interleave phasing to perform power factor correction and voltage regulation. The boost switches are supplied input voltage and input current from a power source. The input voltage is converted to a DC boost voltage by high frequency series interleaved switching of the boost switches. The DC boost voltage is converted to a DC output voltage by the output stage power converter. The DC output voltage is provided on a DC rail for a load of the power factor correcting power supply.

Series interleaved boost converter power factor correcting power supply

The present invention provides a semiconductor device including a memory that has a memory cell array including a plurality of memory cells, a control circuit that controls the memory, and an antenna, where the memory cell array has a plurality of bit lines extending in a first direction and a plurality of word lines extending in a second direction different from the first direction, and each of the plurality of memory cells has an organic compound layer provided between the bit line and the word line. Data is written by applying optical or electric action to the organic compound layer.

Semiconductor device and driving method of the same

Disclosed are various embodiments of voltage protectors that include a first voltage clamping device configured to clamp a voltage of an input power applied to an electrical load, and a second voltage clamping device configured to clamp the voltage applied to the electrical load. A series inductance separates the first and second voltage clamping devices. Also, a switching element is employed to selectively establish a direct coupling of the input power to the electrical load, where a circuit is employed to control the operation of the switching element.

Voltage surge and overvoltage protection

An inrush current limiter for use with an LED driver including a current limiting device, a bypass switch device, and a switch drive. The current limiting device is placed in the input current path of the LED driver to limit input current to a predetermined maximum level in response to an AC conductive angle modulated voltage. The bypass switch device is coupled in parallel with the current limit device. The switch drive turns on the bypass switch device to at least partially bypass the current limiting device as a voltage level of an input of a switching converter rises. The input current remains sufficiently high without exceeding the maximum level. The switch drive is implemented with a delay network driven either by a separate transformer winding or by a snubber network. The delay network may have a delay based on the delay caused by the current limiting device.

Inrush current limiter for an LED driver

An inrush current suppression circuit is installed between a DC voltage and a load with a parallel system capacitor The inrush current suppression circuit includes a first current limiting circuit which includes a first resistor, a first controlled switch, and a second controlled switch The inrush current suppression circuit further includes a second current limiting circuit which further includes a second resistor, a third controlled switch, and an energy-storing capacitor The second current limiting circuit is electrically connected in parallel to the system capacitor, and the first current limiting circuit is electrically connected with the DC voltage and the second current limiting circuit When the DC voltage is detected, the first controlled switch is conducted When a voltage of two ends of the load reaches a first threshold value, the second controlled switch is conducted so as to bypass the first resistor When a voltage of the energy-storing capacitor reaches a second threshold value, the third controlled switch is conducted so as to bypass the second resistor

Inrush current suppression circuit

This research proposed a novel global maximum power point tracking (global-MPPT) algorithm. The proposed algorithm eliminates the perturbation and observation (P&O) technique disturbance problem that the power point will be stuck at the local peak power point under a partial shading condition (PSC). The proposed global-MPPT algorithm detects the photovoltaic module (PV-M) environment irradiance level by the relationship between the output power and voltage of the PV-M. In the proposed algorithm, the important parameter w is determined by the PV-M output power and irradiance level, which is also the compensation parameter that corresponds to the relationship of temperature. The proposed global-MPPT algorithm is aimed to predict the best duty cycle of the global-MPPT based on the irradiance level, parameter w, PV-M output voltage, and load, and then achieve the maximum power point (MPP) quickly and accurately. The measurement results under UIC and PSC verify that the proposed global-MPPT technique performs better than the particle swarm optimization (PSO) and P&O techniques. This research contributes to the proposed method that can find the global-MPP in time based on the irradiance level, temperature, and load.

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Chih-Ming Hsu

Papers

Inrush current suppression circuit

Novel Global-MPPT Control Strategy Considering the Variation in the Photovoltaic Module Output Power and Loads for Solar Power Systems