A semiconductor memory device comprises memory cells, a bitline connected to the memory cells, a read circuit including a precharge circuit, and a first transistor connected between the bitline and the read circuit, wherein a first voltage is applied to a gate of the first transistor when the precharge circuit precharges the bitline, and a second voltage which is different from the first voltage is applied to the gate of the first transistor when the read circuit senses a change in a voltage of the bitline.

Semiconductor memory device.

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Calibration methods and circuits for optimized on-die termination

The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit's input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.

Method and device for transmission with reduced crosstalk

A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited. The first nonvolatile memory area can be prioritized to expedite a read speed of the memory information and the second nonvolatile memory area can be prioritized in guaranteeing the number of times of rewrite operation of memory information more.

Semiconductor Integrated circuit

Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip termination and DC level control that enable an integrated circuit to meet a variety of different high speed single-ended and differential I/O standards.

Programmable termination with DC voltage level control

A semiconductor device is provided which includes: a plurality of termination circuits having a plurality of impedance elements connected to an input/output pad, said termination circuits being controlled by impedance control signals; and a controller for outputting said impedance control signals to adaptively change with changes in characteristic impedance of a transmission line connected to the input/output pad in bi-directional data communication, to adaptively control the plurality of impedance elements in the plurality of input termination circuits for matching the impedance to the characteristic impedance of the transmission line. Each of the plurality of impedance elements is configured in pairs of MOS transistors. The plurality of termination circuits have different impedance values. And each of the impedance elements of the plurality of termination circuits is independently controlled.

Programmable termination circuit and method

A programmable impedance control circuit for detecting a characteristic impedance of transmission line to thereby output it to an output driver and on-chip terminator in a semiconductor device. Particularly the circuit serves to control an internal impedance according to a controlled, programmable protocol irrespective of the changes in an external impedance due to factors such as voltage and temperature after an initial internal impedance is set during a locking operation.

Programmable impedance control circuit and method thereof

An impedance updating apparatus includes a terminator circuit for receiving and terminating an external input signal, the terminator circuit having an up-terminator and a down-terminator; and an update controller for separately controlling the up-terminator and the down-terminator based on the level of the external input signal. The update controller includes at least one latch for latching impedance codes of a programmable impedance controller, the impedance codes being used for controlling transistors in the up-terminator and down-terminator. The update controller performs updating impedance of the up-terminator, or down-terminator when an up-update enable signal or a down-update enable signal and a level of the external input signal correspond to a predetermined condition. And the update controller performs updating impedance of the up-terminator, or down-terminator in response to a level of the external input signal during set-up or hold time only. An impedance updating method of termination circuit having up/down terminators and a separate update controller for detecting terminator through which minimum current flows in response to level of an external input signal is also provided which includes the steps of: determining signal levels of an external input signal to thereby detect a terminator through which minimum current flows between the up or down terminator; and impedance updating the detected terminator through which minimum current flows.

Impedance updating apparatus of termination circuit and impedance updating method thereof

A delay-locked loop (DLL) circuit and a method for generating transmission core clock signals are provided, where the DLL circuit receives an applied external clock signal and generates a transmission core clock signal, the DLL circuit includes a delay circuit unit and a transmission core clock signal generating unit, the delay circuit unit delays the external clock signal through a plurality of delay units configured in a chain type and outputs a plurality of reference clock signals having different phases, the transmission core clock signal generating unit independently selects and controls two reference signals from the plurality of reference clock signals and thus independently generates transmission core clock signals by the number corresponding to ½ times the number of reference clock signals, and the transmission core clock signals have different phases and a period equal to a period of the external clock signal, wherein transmission core clock signals having a precise phase difference are generated individually and independently.

Delay-locked loop circuits and method for generating transmission core clock signals

A semiconductor memory device comprising: an array of memory cells; an address input circuit for receiving an external address in response to an address clock signal; a selecting circuit for selecting a memory cell in response to an address output from the address input circuit; a data output circuit for outputting the data read out from the selected memory cell in response to first and second data clock signals; and an internal clock generating circuit for generating the address clock signal and the first and second data clock signals in response to an external clock signal and a complementary clock signal thereof, wherein the address clock signal and the first and second data clock signals have twice the frequency (or half the period) of the external clock signal when in a test mode

Cho Uk Rae

Papers

Programmable termination circuit and method

Programmable impedance control circuit and method thereof

Impedance updating apparatus of termination circuit and impedance updating method thereof

Delay-locked loop circuits and method for generating transmission core clock signals

Semiconductor memory device capable of generating variable clock signals according to modes of operation