An Inverse Multiplexer is disclosed which first demultiplexes a first data rate input signal into a plurality of second lower data rate subsectional signals, where each subsectional signal is provided with a periodic synchronization marker and includes a data rate which is less than the channel data rate used to transmit that subsectional signal to a remote terminal. Programmable Multiplexers (PMUXs) then operate to each take one or more subsectional signals that are (1) clock synchronized to a PMUX clock, and (2) a rational fraction of the channel data rate, and map contiguously assigned time slots in a capacity domain frame for each subsectional signal to time slots of a time domain frame format using a 2-step or 3-step digit reverse technique. The resultant time domain format has the input subsectional capacity domain time slots substantially uniformly distributed over the time domain frame. At the receiving end, an Inverse Demultiplexer performs the reverse operation to recover the original first data rate input signal.

Inverse multiplexer and demultiplexer techniques

A wireless telecommunications system (1) includes a central terminal (10) for transmitting and receiving radio frequency signals to and from a subscriber terminal (20). A downlink communication path is established from a transmitter (200) of the central terminal (10) to a receiver (202) of the subscriber terminal (20). A downlink signal (212) is transmitted from the transmitter (200) to the receiver (202) during setup and operation of the wireless telecommunications system (1) carrying information partitioned into a plurality of frames. The downlink signal (212) includes an overhead channel (224) having a frame alignment signal (232) for each frame of information. The receiver (202) monitors the downlink signal (212) to identify the frame alignment signal (232). The downlink communication path is established when the receiver (202) identifies two successive frame alignment signals (232). A frame alignment circuit includes a plurality of shift registers (310) arranged in parallel and frame alignment logic (314, 316) for monitoring the shift registers in parallel to identify a frame alignment word and to establish correct frame alignment.

Apparatus and method of frame aligning information in a wireless telecommunications system

Method and apparatus are disclosed for a programmable multiplexer for converting each of one or more input data signals, with individual data rates, into a second higher data rate signal by mapping contiguously arbitarily assigned Capacity Time Slots (CTSs) in a capacity domain frame to Time Slots in a Time Domain frame (TDTSs) so the TDTSs for each input signal are substantially uniformly spread throughout the TD frame. The programmable multiplexer receives separate input data rate signals which are clock synchronized to the multiplexer clock from separate synchronizers, and maps the capacity domain of the input signals to the time frame format using a 2-step or 3-step digit reverse technique. Both techniques decompose the capacity domain address into predetermined digits from predetermined number bases and then combine the digits to perform a similar computation using the number bases in reverse order. The 3-step technique uses an intermediate step of translating the initially determined values for each the predetermined digits using a bit reversal technique.

Programmable multiplexing techniques for mapping a capacity domain into a time domain within a frame

A time division multiplex transmission system includes: a time division multiplex encoder for supplying a master clock to a plurality of PCM digital signal sources having a same sampling frequency and a same quantization bit number to effect clock synchronization and generating a time-divisionally multiplexed data signal based on a data word not D/A converted and sampled from each digital signal source; a transmission line for transmitting the multiplexed data signal from the time division multiplex encoder; and a time division demultiplex decoder for selecting a desired transmitted, multiplexed data signal and demultiplexing the selected data signal in accordance with a transmission rate before the time division multiplexing.

TDM transmission system

Inherent clock information included in a digital signal of the type in which binary information is represented by signal level transistions which are present on a periodic basis, such as a signal level transistion at a mid-location of a bit interval, is recovered by generating a pulse at each signal level transition, delaying that pulse by a half bit interval and by a full bit interval, respectively, and summing the generated, the half bit delayed and the full bit delayed pulses to recover the clock information. The recovered clock is used to write each binary level included in the received digital signal into a memory from which each stored binary level is read at a reference clock rate. Loss of synchronization between the received and read-out digital signals is detected by sensing a differential of predetermined magnitude in the write-in and read-out rates. Preferably, the detected differential in these rates is used to adjust the read clock rate in a direction which tends to null that differential, thereby restoring synchronism between the read out and written in digital signals.

Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal

An aligner (FIG. 1), which has seven registers SRGA to SRGG each of 64 bits in length, is used to align incoming line signals to exchange data rate and to convert exchange rate data signals into line rate data signals. The aligner behaves as a variable delay and is required to operate in any one of three modes; (i) frame aligning 2,048 k Bits/second line signals to a 2,048 k Bits/second exchange rate, (ii) aligning 1,544 k Bits/second line signal to a 2,048 k Bits/second exchange rate and (iii) converting a 2,048 k Bits/second exchange rate to a 1,544 k Bits/second line rate. In the third mode of operation it is necessary to derive the line clock from the exchange local clock. This is achieved by forming a phase-locked loop (FIG. 5) incorporating the delay of a standard aligner and driving the loop with the exchange frame reset signal (f IN).

Frame aligner for use in telecommunications systems

The synchronization arrangement includes a waveform and synchronization information generator to supply synchronization information for transmission with a data stream over digital switching networks. The synchronization information includes two different patterns, phased displaced with respect to each other. Interfaces connect peripheral devices to the networks and are adapted to detect a validate the synchronization information. The checks made are in respect of detecting both patterns, the amount of phase displacement, and the correct sequence. If the synchronization information is invalid, the detecting interface selects a data stream from another network exclusively for use by the corresponding peripheral device.

Chopping Geoffrey

Papers

Frame aligner for use in telecommunications systems

Synchronisation arrangements for a digital telecommunications exchange system

Frame aligner for use in telecommunication exchange systems

Frame aligner in telecommunication systems

Dispositif d'alignement de trames utilisable dans des systemes de telecommunications