This paper presents an integrated mixed-signal 120GHz FMCW/CW radar chipset in a 0.13μm SiGe BiCMOS technology. It features on-chip MMW built-in-self-test (BIST) circuits, a harmonic transceiver, software linearization (SWL) circuits and a digital interface. This chipset has been tested in a low-cost package, where the antennas are integrated. Above 100GHz, our transceiver has achieved state-ofthe-art integration level and receiver linearity, and DC power consumption.

A low-cost miniature 120GHz SiP FMCW/CW radar sensor with software linearization

This paper describes a highly-integrated 122 GHz system-on-chip radar sensor in a SiGe BiCMOS technology. The chip includes a radar transceiver and two on-chip antennas utilizing a novel antenna design approach that allows the use of the localized backside etching technique without compromising the mechanical stability of the chip. The implemented double folded dipole antenna achieves an antenna gain of 6 dBi with a radiation efficiency of 54%. The transceiver is equipped with a 61 GHz VCO that is complemented with a frequency doubler to generate the transmit signal. The receive path includes an LNA, a 90 degree coupler, two passive subharmonic mixers and variable gain amplifiers. Radar measurements with static as well as moving targets were done to show the applicability of the developed system.

Miniaturized 122 GHz system-on-chip radar sensor with on-chip antennas utilizing a novel antenna design approach

This paper presents a frequency quadrupler implemented in a 130nm SiGe:C technology suitable for radar systems with spatially distributed transmitters and receivers. The circuit is based on cascading the bootstrapped Gilbert-Cell doubler topology with differential inputs and differential outputs presented in [1]. In conjunction with a balancing input preamplifier and output buffer amplifier, a maximum power conversion gain of 26 dB and an output power of 0 – 4dBm over 40 GHz (28 %) bandwidth in the range of 120 – 160 GHz is achieved. The frequency quadrupler operates at a power consumption of 132mW with a 1 dB input gain compression point of −22 dBm. The differential output amplitude imbalance in the desired frequency range of 100 – 140 GHz is well below ±1 dB and the preamplifier input match is better than −10 dB between 25 – 35 GHz.

A fully differential 100 – 140 GHz frequency quadrupler in a 130 nm SiGe:C technology for MIMO radar applications using the bootstrapped Gilbert-Cell doubler topology

This paper presents a 61 GHz push-push VCO with an integrated divide-by-eight divider and an output buffer in a 130 nm SiGe BiCMOS process. The VCO core features a differential Colpitts topology with coupled inductors to improve phase noise performance. Eight sub-bands are realized by three digital tuned varicaps, which are placed in parallel with the analog tuned varicap. Its tuning range is 60.85–63.65 GHz with a measured output power of above 10 dBm. The measured phase noise is −106 dBc/Hz at 1 MHz offset with an overall VCO/buffer power dissipation of 93.6 mW. The VCO/buffer has achieved an efficiency of 14%, a figure-of-merit including output power (FOM P ) of 193.1 dBc/Hz and an ITRS FOM of 185.6 dBc/Hz.

A low-phase-noise 61 GHz push-push VCO with divider chain and buffer in SiGe BiCMOS for 122 GHz ISM applications

This paper presents a compact V band Gilbert cell based frequency doubler that generates a truly balanced differential output signal. By analyzing the mechanism causing the imbalanced output in a Gilbert cell based frequency doubler, a Gilbert cell based doubler with a common-mode rejection transformer is designed for V band applications in a 0.13μm SiGe:C HBT process. The doubler delivers about 0.3dBm power at 65GHz, with a 3-dB bandwidth of 20GHz from 55 to 75 GHz, and a power consumption of 50 mW. The measured amplitude imbalance is +0.3/-0.2 dB in the 15GHz bandwidth from 60 to 75GHz.

Compact V band frequency doubler with true balanced differential output

This paper presents an integrated harmonic transmitter front-end for a single-chip 122 GHz FMCW/CW radar sensor It consists of two building blocks, a frequency doubler and a two-directional power detector The frequency doubler employs a push-push frequency doubling core and a common-base stage It exhibits a 25 dB conversion gain and a 5 dBm output power The two-directional power detector is used for self testing, which utilizes a single directional coupler to save chip area and to reduce insertion loss It can detect the output power of the transmitter and can detect any antenna mismatch of above −20 dB This transmitter front-end can be fully characterized by DC measurement after integrated into a single-chip 122 GHz transceiver

http://ieeexplore.ieee.org/iel5/6089237/6102757/06102838.pdf

Christoph J. Scheytt

Papers

An integrated harmonic transmitter front-end for 122 GHz FMCW/CW radar sensor