As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously, work has been done to harden latches against single event upsets (SEU). Currently, there has been a concerted effort to design latches that are tolerant to double node upsets (DNU) and triple node upsets (TNU). In this paper, we first propose a novel DNU tolerant latch design. The latch is designed specifically to provide additional reliability when clock gating is used. Through experimentation, it is shown that the DNU tolerant latch is 11.3 percent more power efficient than existing latch designs suited for clock gating. In addition to the DNU tolerant design, we propose the first TNU tolerant latch. The TNU tolerant latch is shown to provide superior soft error resiliency while incurring a 40 percent overhead compared to DNU tolerant designs.

Radiation Hardened Latch Designs for Double and Triple Node Upsets

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs.

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS

The use of pulse-clocked latches has become ubiquitous in commercial unhardened integrated circuits (ICs) both for their performance and power benefits. In this paper, their use in soft-error hardened triple modular redundant (TMR) circuits is presented. The proposed multi-bit, self-correcting, TMR pulse-clocked latch macro provides a low power, high-speed design with high soft-error immunity. The macro includes test modes for delay testing of both individual and TMR copies with minimal area overhead, as well as a non-redundant operating mode. A physical design flow provides spatial separation of redundant logic copies to avoid upsets due to collection in multiple domains. A TMR, 128-bit data, 256-bit key, advanced encryption standard (AES) is fabricated on a 90-nm foundry low-standby power (LSP) process and its hardness verified using error injection simulations and proton beam testing.

High Performance Low Power Pulse-Clocked TMR Circuits for Soft-Error Hardness

In deep nano-scale and high-integration CMOS technologies, storage circuits have become increasingly sensitive to charge-sharing-induced multiple-node-upsets (MNUs) that include double, triple, and quadruple node-upsets. Currently, verifications for error recovery of existing latches highly rely on EDA tools with complex error-injection combinations. In this article, a latch design protected against MNUs in the harsh radiation as well as an algorithm-based verification process is proposed. Due to the constructed redundant feedback loops, the latch can completely recover from any MNU. Algorithm-based verification and simulations both demonstrate the MNU recovery of the proposed latch. Simulation results demonstrate the low area overhead of the proposed latch compared with the only one existing of the same type.

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation Environments

In modern scaled process technologies a single impinging ionizing radiation particle is increasingly likely to upset multiple circuit nodes and produce logic transients that contribute to the soft error rate. Consequently, hardening flip-flops to transients at the data and control inputs, as well as to single event upsets, due to either single or multi-node upsets is increasingly important. This paper presents a circuit simulation based methodology for pre-layout hardness validation to multi-node upsets. The methodology is applied to the development of a lower power and area radiation hardened flip-flop design, as well as a number of previous hardened flip-flops. Comparison of the hardness, as measured by estimated upset cross-section, is also facilitated. The results also show the importance of specific circuit design aspects to achieving hardness. One of the comparisons to prior designs includes a comparison of the cross-section as determined by the proposed circuit simulation methodology to ion beam results.

Christopher Lieb

Papers

Circuit Simulation Based Validation of Flip-Flop Robustness to Multiple Node Charge Collection