Network architecture, computer system and/or server, circuit, device, apparatus, method, and computer program and control mechanism for managing power consumption and workload in computer system and data and information servers. Further provides power and energy consumption and workload management and control systems and architectures for high-density and modular multi-server computer systems that maintain performance while conserving energy and method for power management and workload management. Dynamic server power management and optional dynamic workload management for multi-server environments is provided by aspects of the invention. Modular network devices and integrated server system, including modular servers, management units, switches and switching fabrics, modular power supplies and modular fans and a special backplane architecture are provided as well as dynamically reconfigurable multi-purpose modules and servers. Backplane architecture, structure, and method that has no active components and separate power supply lines and protection to provide high reliability in server environment.

System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment

System, architecture, and method for logical server and other network devices in a dynamically configurable multi-server network environment

A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.

Method and apparatus for performing multiply-add operations on packed data

Network architecture, computer system and/or server, circuit, device, apparatus, method, and computer program and control mechanism for managing power consumption and workload in computer system and data and information servers Further provides power and energy consumption and workload management and control systems and architectures for high-density and modular multi-server computer systems that maintain performance while conserving energy and method for power management and workload management Dynamic server power management and optional dynamic workload management for multi-server environments is provided by aspects of the invention Modular network devices and integrated server system, including modular servers, management units, switches and switching fabrics, modular power supplies and modular fans and a special backplane architecture are provided as well as dynamically reconfigurable multi-purpose modules and servers Backplane architecture, structure, and method that has no active components and separate power supply lines and protection to provide high reliability in server environment

Apparatus, architecture, and method for integrated modular server system providing dynamically power-managed and work-load managed network devices

Dynamic power and workload management for multi-server system

A linear interpolator and decimating FIR filter with constant coefficients may be used in various configurations to scale a still or moving color video image horizontally (changing the number of pixels per row) or vertically (changing the number of pixels per column). For downscaling, the input pixel stream is initially upscaled with an interpolator by an upscaling factor of between one and two chosen so that the result can be subsequently downscaled with a decimation-by-power-of-two finite impulse response (FIR) filter to provide the desired final scaling. Upscaling is a special case accomplished by means of linear interpolation. Vertical and horizontal scaling may be performed with different, independent scaling factors.

Video scaling method and device

A recoding method of two or more bit groups to reduce the number of partial products and their hardware implementation. Unique complementing scheme, pre-addition of complementing carriers and derivation of sign extensions also reduce hardware implementation as well as allowing the multiplier to handle any combination of input and output formats. The principles are also applied to multiplier/accumulators and complex multipliers.

Plural-bit recoding multiplier

A memory having at least a pair of cache registers between the data input and output ports and the read and write ports of a memory matrix and controls to alternate the interconnection between the cache registers and the data input/output ports and the read/write terminals of the memory matrix, such that while one cache register is connected to the data input/output port, the other cache register is connected to a port of the memory. Look-ahead logic is provided to generate the next address of the memory location which is to be written into or read from with simultaneous transfer of information to or from the cache register which is connected to the memory ports.

Memory with cache register interface structure

A modular matrix processor which is capable of configuration as a stand alone symmetrical kernel convolutor or one of plural cascaded asymmetrical kernel convolutors. The module includes coefficient registers and associated multipliers to multiply sequential pixels or words by an appropriate coefficient. A summer, with appropriate input delays, sums the products and provides them to a plurality of FIFO (first in - first out) for storing the sums per row. An adder adds the contents of the summer, FIFO's and cascaded inputs to provide a convolution output Pc. Plural frames may be processed using the pixel input, coefficient input and cascade inputs. Plural modules may be used per row to increase the kernel size as well as the row capacity of the FIFO's.

East image processing accelerator for real time image processing applications

A square root is calculated by performing a plurality of iterations of the following: X(n+1)=X(0)+X(n)* X(n)* 2.sup.-0.5*max-1 wherein X(0) is the seed value, max is the weight of the most significant bit of the smallest perfect binary square higher than the most significant bit of the operand A and calculating the square root R as follows: R=2.sup.0.5*max -X(last) The seed value, or X(0) is calculated as follows: x(0)=(2.sup.max -A) * 2.sup.-0.5*max-1 To increase the accuracy and reduce the error, the operand can be initially upscaled and then downscaled in the final operation.

Christopher W. Malinowski

Papers

Video scaling method and device

Plural-bit recoding multiplier

Memory with cache register interface structure

East image processing accelerator for real time image processing applications

Method and apparatus for computing square roots of binary numbers