The present disclosure relates to envelope power supply calibration of a multi-mode RF power amplifier (PA) to ensure adequate headroom when operating using one of multiple communications modes. The communications modes may include multiple modulation modes, a half-duplex mode, a full-duplex mode, or any combination thereof. As such, each communications mode may have specific peak-to-average power and linearity requirements for the multi-mode RF PA. As a result, each communications mode may have corresponding envelope power supply headroom requirements. The calibration may include determining a saturation operating constraint based on calibration data obtained during saturated operation of the multi-mode RF PA. During operation of the multi-mode RF PA, the envelope power supply may be restricted to provide a minimum allowable magnitude based on an RF signal level of the multi-mode RF PA, the communications mode, and the saturation operating constraint to provide adequate headroom.

Envelope power supply calibration of a multi-mode radio frequency power amplifier

A direct current (DC)-DC converter that includes a first switching converter and a multi-stage filter is disclosed. The multi-stage filter includes at least a first inductance (L) capacitance (C) filter and a second LC filter coupled in series between the first switching converter and a DC-DC converter output. The first LC filter has a first LC time constant and the second LC filter has a second LC time constant, which is less than the first LC time constant. The first switching converter and the multi-stage filter form a feedback loop, which is used to regulate the first switching power supply output signal based on the setpoint. The first LC filter includes a first capacitive element having a first self-resonant frequency, which is about equal to a first notch frequency of the multi-stage filter.

Direct current (DC)-DC converter having a multi-stage output filter

An automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention.

Auto configurable 2/3 wire serial interface

DC to DC converter circuitry includes a dual phase charge pump and at least one pair of multiplier phase circuits. The dual phase charge pump is coupled to each one of the at least one pair of multiplier circuits and adapted to receive a DC input voltage and only four control signals, and produce a stepped-up output voltage. Each one of the at least one pair of multiplier phase circuits are adapted to receive the stepped-up output voltage, a cross-coupled control signal from the other multiplier phase circuit in the pair of multiplier phase circuits, and a different one of the control signals and further multiply the stepped-up output voltage to produce a multiplied stepped-up output voltage with a magnitude that is approximately three times that of the DC input voltage or greater.

Voltage multiplier charge pump buck

Embodiments of the present disclosure relate to an overlay class F choke of a radio frequency (RF) power amplifier (PA) stage and an RF PA amplifying transistor of the RF PA stage. The overlay class F choke includes a pair of mutually coupled class F inductive elements, which are coupled in series between a PA envelope power supply and a collector of the RF PA amplifying transistor. In one embodiment of the RF PA stage, the RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. The collector of the RF PA amplifying transistor provides the RF stage output signal. The PA envelope power supply provides an envelope power supply signal to the overlay class F choke. The envelope power supply signal provides power for amplification.

Overlay class f choke

A power supply apparatus includes an open loop power switcher, a power isolation transformer, a backlight driving circuit, and a power circuit. The open loop power switcher converts a direct current (DC) power into an alternating current (AC) input voltage. The power isolation transformer is coupled to the open loop power switcher and includes a primary-side winding, a first winding, and a second winding, wherein the first and second windings are disposed at the secondary-side of the power isolation transformer, and the first winding is employed for generating a first voltage signal according to the AC input voltage. The backlight driving circuit is employed for driving a backlight module according to the first voltage signal. The power circuit is employed for receiving a second voltage signal generated from the second winding according to the AC input voltage, in order to generate an output power signal.

Chung-Chih Chen

Papers

Power supply apparatus