Advancing zero defect manufacturing: A state-of-the-art perspective and future research directions

In this work, we utilized a digital integrated-circuit (IC) testing model (DITM), based on a statistical simulation method, to evaluate the test yield and test quality of semiconductor prod...

Test yield and quality analysis models of chips

This study aims to exploit an integrated-circuit (IC) testing model based on a statistical simulation method to evaluate the test yield and quality of IC products. Using normal probability distributions of product properties, we digitally analyzed IC yield and quality, introduced testing threshold and guardband, and assessed various parameters’ influence on outcomes. Because future manufacturing speed is unpredictable, we used current manufacturing technology and existing-product electrical properties to estimate future product-distribution trends. Since the progress of developmental improvements for testing technologies has been slow, it has become a greater challenge for a supplier to determine the use of existing instruments and tools to achieve quality products with near-zero defects. To improve product quality, a new scheme of Multiple tests has been proposed. Moreover, we used a set of parameters from the International Technology Roadmap for Semiconductors (ITRS) to demonstrate the proposed Multiple testing, and to show that the test yield can be improved while attaining the desired quality.

The Decision Mechanism Uses the Multiple-Tests Scheme to Improve Test Yield in IC Testing

In this work, we use statistical concepts to evaluate the joint probability distribution of manufacturing and test parameters and estimate the future trend of wafer test yield. Owing to the difference between the development speeds of testing technology and manufacturing technology, the testing capability of wafers is far behind the manufacturing capability of the semiconductor. Therefore, with the advancement in technology, the test yield loss caused by the tester inaccuracy has become an important problem. In this article, we propose an enhanced integrated circuit (IC) test scheme (ITS) that uses multiplex testing to improve test quality and test pass rate by retesting, and we rely on the cost evaluation mechanism to obtain the best test and the best profit. Furthermore, the International Roadmap for Devices and Systems (IRDS) 2017 data are used to estimate future test yield trends, and the results prove that the enhanced test scheme (ETS) can effectively estimate the best retest time to obtain the best test yield and the best profit.

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Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

Developing a hybrid data-fitting procedure and a case study for patient service time

The ultimate goal for all manufacturing industries is to construct products with zero defects and high quality to improve customer satisfaction. For the automotive electronics industry, which tends to have higher standards with regard to safety, the requirements for quality are particularly strict. Since most test quality cannot satisfy the demands of the automobile electronics market currently, suppliers must re-evaluate their testing programs to find a more cost-effective alternative to current testing methods. In this study, a probability concept is proposed, which assumes a normal distribution as the product characteristic. The manufacturing and testing are also quantified, where a model is introduced for test quality and test yield in order to improve the value with regard to digital IC testing. However, the speed of progress in manufacturing in the future is unpredictable, so we had to make use of current manufacturing technology and existing products’ electrical properties to predict future trends in product distribution. A valid repeat testing method was proposed simultaneously, where the moving guard-band test was used, so that the test yield and test quality could be improved to achieve high-quality requirements and zero defect goals that are essential for aviation and biomedical electronics products. The repeated testing methodology found in Table B (Overall Roadmap Technology Characteristics) of the International Technology Roadmap for Semiconductors (ITRS 1999 and 2015) was repeated here to help improve the test yield and desired quality.

Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements

Editor’s notes: Tester inaccuracies can cause even good chips to fail manufacturing test. This article discusses a recycling test method in which failing chips are tested again under appropriate conditions to reduce the yield loss while still maintaining acceptable test time. —Jennifer Dworak, Southern Methodist University

Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments

In the past 20 years, semiconductor manufacturing technology has advanced rapidly, but the advancement of integrated circuit (IC) testers has been slow. Using obsolete testers to inspect advanced wafers has become a significant challenge for test manufacturers. In this research, we used DITM (digital IC testing model) to discuss the impact of the test guardband (TGB) on quality and yield. Considering the interaction between semiconductor fabrication capability parameters and test capability parameters, we proposed an estimation method [deductive estimation method (DEM)] to analyze the electrical distribution changes of products after chip production and deduce the yield of future products. The deductive estimation method can correctly depict the future test yield [Formula: see text] curve using the chip frequency data published by IRDS (International Roadmap for Devices and Systems) in 2017. Furthermore, test manufacturers can measure whether the current test capabilities can cope with future semiconductor chip manufacturing capabilities by predicting the trends. Next, test manufacturers can maintain high-quality and high-yield chip output by pre-adjusting the hardware testing capabilities of ATE (automated test equipment) or proposing more effective chip testing methods. 

Chung Huang Yeh

Papers

Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements

Test yield and quality analysis models of chips

Using Enhanced Test Systems Based on Digital IC Test Model for the Improvement of Test Yield

Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments

Predict the Test Yield of Future Integrated Circuits through the Deductive Estimation Method