C
Chung-Wen Albert Tsao
Researcher at University of California, Los Angeles
Publications - 7
Citations - 235
Chung-Wen Albert Tsao is an academic researcher from University of California, Los Angeles. The author has contributed to research in topics: Routing (electronic design automation) & Elmore delay. The author has an hindex of 6, co-authored 7 publications receiving 227 citations.
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Proceedings ArticleDOI
On the Bounded-Skew Clock and Steiner Routing Problems
TL;DR: This work provides unifications of the clock routing and Steiner tree heuristic literatures and gives smooth cost-skew tradeoff that enable good engineering solutions.
Journal ArticleDOI
Old Bachelor Acceptance: A New Class of Non-Monotone Threshold Accepting Methods
TL;DR: Experiments using several classes of symmetric traveling salesman problem instances show that OBA can outperform previous hill-climbing methods for time-critical optimizations.
Journal ArticleDOI
Planar-DME: a single-layer zero-skew clock tree router
TL;DR: This paper presents new single-layer, i.e., planar-embeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model, and substantially improve over previous planar clock routing methods.
Proceedings ArticleDOI
Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay
TL;DR: From this, a top-down algorithm is developed which dynamically determines and embeds the clock tree topology, such that the embedding is guaranteed to be planar and the result has provably minimum total wirelength and minimum pathlength delay for that topology.
Proceedings ArticleDOI
Low-cost single-layer clock trees with exact zero Elmore delay skew
TL;DR: In this paper, a single-layer clock tree construction with exact zero skew according to the Elmore delay model is presented. But the tree is constructed using a linear-planar-DME variant connection topology.