We present RayCore, a mobile ray-tracing hardware architecture. RayCore facilitates high-quality rendering effects, such as reflection, refraction, and shadows, on mobile devices by performing real-time Whitted ray tracing. RayCore consists of two major components: ray-tracing units (RTUs) based on a unified traversal and intersection pipeline and a tree-building unit (TBU) for dynamic scenes. The overall RayCore architecture offers considerable benefits in terms of die area, memory access, and power consumption. We have evaluated our architecture based on FPGA and ASIC evaluations and demonstrate its performance on different benchmarks. According to the results, our architecture demonstrates high performance per unit area and unit energy, making it highly suitable for use in mobile devices.

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RayCore: A Ray-Tracing Hardware Architecture for Mobile Devices

We propose a novel massively parallel construction algorithm for Bounding Volume Hierarchies (BVHs) based on locally-ordered agglomerative clustering. Our method builds the BVH iteratively from bottom to top by merging a batch of cluster pairs in each iteration. To efficiently find the neighboring clusters, we keep the clusters ordered along the Morton curve. This ordering allows us to identify approximate nearest neighbors very efficiently and in parallel. We implemented our algorithm in CUDA and evaluated it in the context of GPU ray tracing. For complex scenes, our method achieves up to a twofold reduction of build times while providing up to 17 percent faster trace times compared with the state-of-the-art methods.

Parallel Locally-Ordered Clustering for Bounding Volume Hierarchy Construction

Ray tracing has long been considered as the next-generation technology for graphics rendering. Recently, there has been strong momentum to adopt ray tracing--based rendering techniques on consumer-level platforms due to the inability of further enhancing user experience by increasing display resolution. On the other hand, the computing workload of ray tracing is still overwhelming. A 10-fold performance gap has to be narrowed for real-time applications, even on the latest graphics processing units (GPUs). As a result, hardware acceleration techniques are critical to delivering a satisfying level performance while at the same time meeting an acceptable power budget. A large body of research on ray-tracing hardware has been proposed over the past decade. This article is aimed at providing a timely survey on hardware techniques to accelerate the ray-tracing algorithm. First, a quantitative profiling on the ray-tracing workload is presented. We then review hardware techniques for the main functional blocks in a ray-tracing pipeline. On such a basis, the ray-tracing microarchitectures for both ASIC and processors are surveyed by following a systematic taxonomy.

Toward Real-Time Ray Tracing: A Survey on Hardware Acceleration and Microarchitecture Techniques

Ray-tracing algorithms are known for producing highly realistic images, but at a significant computational cost. For this reason, a large body of research exists on various techniques for accelerating these costly algorithms. One approach to achieving superior performance which has received comparatively little attention is the design of specialised ray-tracing hardware. The research that does exist on this topic has consistently demonstrated that significant performance and efficiency gains can be achieved with dedicated microarchitectures. However, previous work on hardware ray-tracing has focused almost entirely on the traversal and intersection aspects of the pipeline. As a result, the critical aspect of the management and construction of acceleration data-structures remains largely absent from the hardware literature.We propose that a specialised microarchitecture for this purpose could achieve considerable performance and efficiency improvements over programmable platforms. To this end, we have developed the first dedicated microarchitecture for the construction of binned SAH BVHs. Cycle-accurate simulations show that our design achieves significant improvements in raw performance and in the bandwidth required for construction, as well as large efficiency gains in terms of performance per clock and die area compared to manycore implementations. We conclude that such a design would be useful in the context of a heterogeneous graphics processor, and may help future graphics processor designs to reduce predicted technology-imposed utilisation limits.

A hardware unit for fast SAH-optimised BVH construction

We present a hybrid architecture, inspired by asynchronous BVH construction [1] , for ray tracing animated scenes. Our hybrid architecture utilizes heterogeneous hardware resources: dedicated ray-tracing hardware for BVH updates and ray traversal and a CPU for BVH reconstruction. We also present a traversal scheme using a primitive’s axis-aligned bounding box (PrimAABB). This scheme reduces ray-primitive intersection tests by reusing existing BVH traversal units and the primAABB data for tree updates; it enables the use of shallow trees to reduce tree build times, tree sizes, and bus bandwidth requirements. Furthermore, we present a cache scheme that exploits consecutive memory access by reusing data in an L1 cache block. We perform cycle-accurate simulations to verify our architecture, and the simulation results indicate that the proposed architecture can achieve real-time Whitted ray tracing animated scenes at $1{,}920\;\times\;1{,}200$ resolution. This result comes from our high-performance hardware architecture and minimized resource requirements for tree updates.

HART: A Hybrid Architecture for Ray Tracing Animated Scenes

Traversing an acceleration data structure, such as the Bounding Volume Hierarchy or kD-tree, takes a significant amount of the total time to render a frame in real-time ray tracing. We present a two-phase algorithm based upon the Multi Level Ray-Tracing Algorthm (MLRTA) for finding deep entry points in these tree acceleration data structures in order to speed up traversal. We compare this algorithm to a base MLRTA implementation. Our results indicate an across-the-board decrease in time to find the entry point and deeper entry points. The overall performance of our real-time ray-tracing system shows an increase in frames per second of up to 36% over packet-tracing and 18% over MLRTA. The improvement is algorithmic and is therefore applicable to all architectures and implementations.

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Accelerated entry point search algorithm for real-time ray-tracing

The ray tracing algorithm is known primarily for producing highly realistic images, but also for its high computational cost. Perhaps the most effective method for accelerating ray tracing is through the use of spatial index structures, such as kd-trees and bounding volume hierarchies. In highly dynamic scenarios, these structures must be rebuilt frequently, constituting a considerable portion of the total time to image.

Hardware accelerated construction of SAH-based bounding volume hierarchies for interactive ray tracing

The strive towards realistic simulations at interactive speeds has driven research in both rendering and physical simulation. This heightened realism involves larger data sets and data structures, and comes at a high computational cost. We investigate simulations involving collision detection and real-time ray-tracing and note similarities in the data structures used to accelerate them. Our investigation demonstrates that it is possible to utilize a single Acceleration Data Structure (ADS) for both subsystems of an interactive simulation, even though they benefit from different characteristics. Typically, the collision detection and ray-tracing system build ADSs that satisfy their specific needs. We argue for a shared adaptive ADS that can be optimized for both collision detection and ray-tracing. The collision detection system builds this adaptive ADS and the ray-tracing algorithm uses the same adaptive ADS after the collision detection system has resolved potential collisions, therefore saving memory, execution time and power. The results show that compromises need not be made on build heuristics. Furthermore, the ADS may be optimized for primary and secondary rays and consequently save more memory, execution time and large quantities of power.

Colin Fowler

Papers

A hardware unit for fast SAH-optimised BVH construction

Accelerated entry point search algorithm for real-time ray-tracing

Hardware accelerated construction of SAH-based bounding volume hierarchies for interactive ray tracing

Adaptive BVH: an evaluation of an efficient shared data structure for interactive simulation