Systems and methods for improving or suggesting alternatives to content surfing are provided. When it is detected that a user wishes to surf, a pipeline tuning sequence is implemented where by storing one or more frames of a first content selection to the user equipment and acquiring a subsequent content selection while concurrently displaying the previously stored one or more frames. Content suggestions, program listing grids, media guidance application and tuning hints, advertisements, digital audio, and live video may also be presented to user while content surfing. In some embodiments, content surf landing channels may be anticipated based on user history, user profiles, or any other suitable information. In some embodiments, thumbnails of the user's recently tuned, or paused on, content are displayed to the user while content surfing. In multiple tuner systems, more than one thumbnail may be displayed in full motion video.

Systems and methods for content surfing

In one embodiment, a multicore processor includes a controller to dynamically limit a maximum permitted turbo mode frequency of its cores based on a core activity pattern of the cores and power consumption information of a unit power table. In one embodiment, the core activity pattern can indicate, for each core, an activity level and a logic unit state of the corresponding core. Further, the unit power table can be dynamically computed based on a temperature of the processor. Other embodiments are described and claimed.

Dynamically computing an electrical design point (edp) for a multicore processor

A data module operable in a wireless communication system is provided. The data module comprises a plurality of circuit components, one or more temperature sensors, and a thermal management unit. The temperature sensors are configured to determine the temperature of a corresponding circuit component. The thermal management unit is configured to determine one or more thermal characteristics of the data module based on the temperature determinations, and to generate one or more power control point signals indicating whether to adjust corresponding operating characteristics of a target component based on the determined thermal characteristics.

Thermal management for data modules

A system for storing encrypted compressed data comprises a processor and a memory The processor is configured to determine whether an encrypted compressed segment has been previously stored The encrypted compressed segment was determined by breaking a data stream, a data block, or a data file into one or more segments and compressing and then encrypting each of the one or more segments The processor is further configured to store the encrypted compressed segment in the event that the encrypted compressed segment has not been previously stored The memory is coupled to the processor and configured to provide the processor with instructions

Segment deduplication system with encryption and compression of segments

A multi-core microprocessor provides an indication of the power management state of each of the cores on output terminals. Cooling of the cores is adjusted responsive to the indication of the power management state of the respective cores with additional cooling being provided to those cores in a more active state and less cooling provided to those cores in a less active state.

Heat management using power management information

In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the operations for which the integrated circuit is designed. The power manager is configured to transmit a power supply voltage request to an external power supply module, the power supply voltage request indicating a requested magnitude of the power supply voltage for the integrated circuit. The power manager is configured to modify the requested magnitude responsive to indications from each of the plurality of temperatures sensors that represent a temperature of the integrated circuit sensed by each of the plurality of temperature sensors.

Temperature compensation in integrated circuit

In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.

Power switch ramp rate control using daisy-chained flops

A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.

Regional clock gating and dithering

In an embodiment, an integrated circuit includes a power gated block and a power manager circuit The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner The power gated block may control the rate at which power switches are enabled based on the select signal or signals For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled

Power switch ramp rate control using programmable connection to switches

In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

Conrad H. Ziesler

Papers

Temperature compensation in integrated circuit

Power switch ramp rate control using daisy-chained flops

Regional clock gating and dithering

Power switch ramp rate control using programmable connection to switches

Dynamic voltage margin recovery