An apparatus and method for a low voltage drop and thermally enhanced integrated circuit (IC) package are described. A substantially planar substrate having a plurality of contact pads on a first surface is electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate. An IC die having a first surface is mounted to the first surface of the substrate. The IC die has a plurality of I/O pads electrically connected to the plurality of contact pads on the first surface of the substrate. A heat sink assembly is coupled to a second surface of the IC die and to a first contact pad on the first surface of the substrate to provide a thermal path from the IC die to the first surface of the substrate. The heat sink assembly can also provide an electrical path from the IC die to the first surface of the substrate. The heat sink assembly may have one or two heat sink elements to provide thermal and/or electrical connectivity between the IC die and the substrate.

Low voltage drop and high thermal performance ball grid array package

Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. A substrate has a surface, wherein the surface has an opening therein. A stiffener has a surface coupled to the surface of the substrate. An area of the surface of the stiffener can be greater than, equal to, or less than an area of the surface of the substrate. A thermal connector is coupled to the surface of the stiffener through the opening. A surface of the thermal connector is capable of attachment to a printed circuit board (PCB) when the BGA package is mounted to the PCB. The thermal connector can have a height such that the thermal connector extends into a cavity formed in a surface of the PCB when the BGA package is mounted to the PCB. Alternatively, the stiffener and thermal connector may be combined into a single piece stiffener, wherein the stiffener has a protruding portion. The protruding portion extends through the opening when the stiffener is coupled to the substrate, and is capable of attachment to the PCB.

Ball grid array package enhanced with a thermal and electrical connector

Electrically, mechanically, and thermally enhanced ball grid array (BGA) packages are described. An IC die is mounted in a centrally located cavity of a substantially planar first surface of a stiffener. The first surface of a substrate is attached to a substantially planar second surface of the stiffener. The second surface of the stiffener is opposed to the first surface of the stiffener. A centrally located protruding portion on the second surface of the stiffener is opposed to the centrally located cavity. The protruding portion extends through an opening in the substrate. A wire bond is coupled from a bond pad of the IC die to a contact pad on the first surface of the substrate through a through-pattern in the stiffener. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, a notch in an edge of the recessed portion, and a notch in an edge of the opening.

Ball grid array package with patterned stiffener layer

An apparatus, system, and method for assembling a ball grid array (BGA) package is described. A stiffener/heat spreader is provided. A substrate has a first surface and a second surface. The substrate has a central window-shaped aperture that extends through the substrate from the first substrate surface to the second substrate surface. The first substrate surface is attached to a surface of the stiffener/heat spreader. A portion of the stiffener/heat spreader is accessible through the central window-shaped aperture. An IC die has a first surface and a second surface. The first IC die surface is mounted to the accessible portion of the stiffener/heat spreader. A drop-in heat spreader has a surface that is mounted to the second IC die surface.

Enhanced die-down ball grid array and method for making the same

An integrated circuit (IC) device package is presented. A frame body has opposing first and second surfaces and a central opening that is open at the first and second surfaces. The second frame body surface is mounted to a first stiffener surface. An IC die is mounted to the first stiffener surface within the central opening through the frame body. A planar lid has opposing first and second surfaces. The second lid surface is coupled to the first frame body surface. A first substrate surface is coupled to a second stiffener surface. An array of electrically conductive terminals is coupled to a second substrate surface. The stiffener, frame body, and lid form an enclosure structure substantially enclosing the IC die. The die enclosure spreads heat from the IC die, and shields EMI emanating from and radiating toward the IC die. At least one tab protrudes from the second surface of the frame body. At least one receptacle formed in the first surface of the stiffener corresponding to the at least one tab. The at least one tab is coupled with the at least one corresponding receptacle, whereby structural coupling of said frame body to said stiffener is substantially improved.

Multipiece apparatus for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages and method of making the same

The application of a controlled-collapse chip connection (C4), ceramic-ball-grid array (CBGA) single-chip package to the Motorola 88110 RISC CMOS microprocessor is presented. Also presented are the zero-level to second-level interconnection technologies and the various design considerations: from the on-chip redistribution metal to the printed-circuit board definition. In addition to an overview of the interconnect technology, we discuss the: (1) printed-circuit board design, (2) first-level and second-level assembly, (3) electrical modeling and characterization, (4) thermal management, and (5) controlled-collapse chip connection (C4) and ceramic-ball-grid array (CBGA) interconnection reliability and solder-fatigue life estimates. For this study four discipline-specific technology test vehicles were used to evaluate the assembly, electrical, thermal, and reliability aspects of this C4/CBGA interconnect technology. The design and use of each test vehicle is presented. In contrast to a 51 mm, wirebond pin-grid array package (PGA), the C4/CBGA package offers several technological improvements for high-performance RISC microprocessors, which are: (1) a much smaller use of printed-circuit board area, for example, the 361 I/O 25 mm package reduces the original package footprint by approximately 75%, (2) a surface mountable package, (3) the package-to-board assembly is possible with industry-standard surface-mount equipment, (4) the use of C4 and CBGA technology reduce the electrical parasitics, (5) the junction-to-cap thermal resistance was less than 1.5/spl deg/C/W, and (6) the CBGA solder joints are predicted to exceed 3,500 on/off cycles, of 25/spl deg/C to 55/spl deg/C cycling, with a failure rate of 100 parts per million (ppm) per package.

A hi-density C4/CBGA interconnect technology for a CMOS microprocessor

The Motorola PowerPC 603 and PowerPC 604 microprocessors are available in the 21 mm controlled-collapsed-chip-connection/ceramic-ball-grid-array single-chip package (C4/CBGA). This paper will introduce the C4/CBGA interconnect technology and address the following: (1) the PCB land definition and board preparation requirements, (2) the ball-grid-array to board assembly methods, (3) the electrical design considerations, (4) the heat transfer mechanism and thermal control options, and (5) the CBGA-to-PCB testing and reliability.

D. Gerke

Papers

A hi-density C4/CBGA interconnect technology for a CMOS microprocessor

Motorola's PowerPC 603 and PowerPC 604 RISC microprocessor: the C4/ceramic-ball-grid array interconnect technology