We have devised and tested a planar coupling scheme in which the technology used to produce ultra low noise tunnel junction dc SQUIDs is employed to achieve tight coupling between the SQUID loop and and the input coil. In our scheme the planar, ungroundplaned, inductive loop of the dc SQUID acts as the wide single turn primary of a thin-film transformer. The input coil consists of a multiple-turn secondary in the form of a spiral stripline fabricated directly above the primary. The two tunnel junctions are located at the outside edge of the SQUID loop. A low inductance stripline structure connects the junctions to the region of high current flow in the SQUID loop. We have evaluated this coupling scheme experimentally in SQUIDs with 10-turn, 19-turn, 50-turn, and 100-turn input coils. All have mutual inductances per turn of approximately 80 pH, in good agreement with numerical calculations. Detailed measurements on the 50-turn SQUID gave a mutual inductance M of 3.8 nH, an input coil inductance L i of 190 nH, a SQUID self inductance of L of 89 pH, and a coupling constant k2= M2/L i L of 0.86. The 100- turn version is estimated to have similar coupling performance with an input coil inductance of approximately 0.8 μH.

Planar coupling scheme for ultra low noise DC SQUIDs

The four primary areas of concern in the development of high performance dc SQUIDs are white noise, 1/f noise, readout schemes, and coupling. For an optimized dc SQUID the intrinsic energy sensitivity in the white noise region is given by e w =γ 1 hk B T(eI 0 R)-1+γ 2 h, where I o is the critical current per junction and R is the shunt resistance per junction. γ 1 , which multiplies the thermal noise contribution, and γ 2 , which multiplies the shot noise/zero point fluctuation contribution, are numerical factors of order unity. Values of e w approaching h have recently been measured for several members of a new generation of low noise dc SQUIDs. The intrinsic energy sensitivity in the 1/f noise region, e f , is predicted to scale as (I 0 R)2for tunnel junctions. This may impose significant low frequency limitations on SQUIDs with very low values of e w . Readout schemes for high sensitivity dc SQUIDs will require further development. At the moment primarily small signal amplifier readout schemes are being used to evaluate the new generation of low noise SQUIDs. Planar thin-film coupling schemes are about to have a big impact on dc SQUID design. Such schemes can achieve tight coupling between SQUID and input coil. and can be implemented using the same fabrication techniques that produce SQUIDs with low values of e w .

DC SQUIDs 1980: The state of the art

A family of novel Josephson logic circuits called current injection logic (CIL) is presented. In contrast to previous approaches, it combines magnetically coupled interferometers with novel nonlinear injection gates to obtain ultra-fast logic speeds, wide margins, and greater fan-in and fan-out capabilities. Fastest logic delay of 30 ps/gate is measured averaged over two- and four-input OR and AND gates (average fan-in=4.5, average fan-out=2.5) fabricated using 2.5 /spl mu/m nominal design rules. The average power dissipation of these experimental circuits is 6 /spl mu/W/gate. An unprecedented logic delay of 13 ps/stage is measured on a chain of two-input OR gates, and the logic delay for a circuit consisting of two two-input OR gates, the outputs of which are `AND'ed, is measured at 26 ps. The experimental results are found to be in excellent agreement with delay estimates based upon computer simulations.

A 30-ps Josephson current injection logic (CIL)

A review of the recent advances in Josephson logic devices and circuits is presented. The Josephson junction is almost an ideal digital switch exhibiting very abrupt threshold, ultra-high switching speeds (∼10 ps), and very low power dissipation (∼1 µW). Logic devices based on the Josephson junctions combine Josephson junctions with other circuit elements to provide isolation to the input signals as well as to provide higher gain than a single junction. These devices can be classified into two groups, the first group uses magnetically coupled SQUID's (Superconducting QUantum Interference Devices) to provide isolation, whereas the second group of circuits utilizes the high-resistance state of a Josephson junction in series with the signal input to provide isolation. Logic circuits based on these two isolation Schemes are compared. In both schemes, higher gains are achieved by the use of either multiple Josephson junctions in parallel or a buffer stage. The buffer stage is a Current-Injection Device (CID) which provides gain and the AND function between the two signal currents injected into it. Some of the unique features of Josephson logic circuits such as terminated superconducting transmission lines, ac power supply, Timed Inverter, and Latch circuits are also examined. The dynamic behavior of the Josephson junctions is modeled by very simple equivalent circuits. The computer simulations based on these models are compared with experiments and found to be in excellent agreement. A family of experimental logic circuits has been designed and experimentally tested using 2.5-µm minimum feature size. These circuits have fully loaded logic delays of about 40 ps/gate and power dissipation of about 4 µW/gate. The gate delays and power-delay products are compared with leading semiconductor technologies.

Josephson-logic devices and circuits

Recent progress in Josephson digital logic circuits is described. It is noted that changing the junction material from a lead alloy to niobium has dramatically improved process reliability, and that high-speed, low-power operations have been demonstrated at large-scale integrated-circuit levels. The first Josephson microprocessor, operated at 770 MHz, verified the potential of Josephson devices for future digital elements. The possibilities of the ultrafast Josephson computer, previously shelved because of a number of problems, are being actively reconsidered. The performance anticipated for Josephson digital circuits using high-temperature superconducting materials is also discussed. >

Digital logic circuits

We have developed an ac power distribution scheme which provides switched regulated power of alternating polarity (no rectification necessary) for Josephson interferometer latching logic circuits. Distribution from the power source relies on a tree system of thin film transformers having single primaries and multiple secondaries to maintain low current levels and small phase skews throughout the system. Power signals are clipped on chip to the desired voltage supply level by series connected large area Josephson junctions ("regulator" junctions) and distributed across the chip by voltage busses. Supply resistors between the regulated voltage bus and the logic circuits define the operating current level. A detailed design is presented for a specific interferometer latching circuit family. We report experimental data on the two major components of the power system design - the regulators and the transformers. A series string of four regulator junctions provides a trapezoidal waveform of 11 mV amplitude at > 66% logic duty cycle (that portion of the machine cycle in which logic operations can be performed). Thin film transformers have their designed inductance (350 pH) and coupling coefficient ( > .90).

D. Herrell

Papers

Regulated AC power for Josephson interferometer latching logic circuits