In some embodiments, the invention involves saving limited context information when transitioning between virtual machines. A predetermined set of instructions and events cause a trap. A bit or flag is set to indicate that the event has occurred within a virtual machine. The virtual machine monitor determines whether specific register sets must be saved or restored upon a context switch, based on whether the flag has been set. Other embodiments are described and claimed.

System and method to optimize os context switching by instruction group trapping

A method of producing a computer program for a computer capable of operating in a plurality of disjoint instruction sets. The method produces a plurality of independently callable functions. For each function the method determines a target instruction set employed by the function. The method provides the function with a name corresponding to the target instruction set. The function name is preferably a modification of a user provided function name corresponding to the target instruction set. The method identifies each call of another independent function and provides each with a name corresponding to the target instruction set. The method produces a veneer function for each function and for each other instruction set. The veneer functions include changing the computer from operating in the other instruction set to operating in the target instruction set, calling the corresponding function, changing the computer to operate in the other instruction set, and a return command. Each veneer function is provided with a name corresponding to the other instruction set. Each function and its corresponding veneer functions are converted into a linkable object code module and then linked into an executable object code file of the computer program. The linker preferably omits from the executable object code file any veneer functions not called by a function.

Maintaining code consistency among plural instruction sets via function naming convention

Exploiting large register sets

An architecture is proposed that allows fast procedure calls, low-overhead task switches, and primitives, which assist in queue-oriented intertask communications. This is accomplished by managing the registers as noncontiguous register windows. The details of the register granularity are hidden from the applications program. The architecture is based on a VLSI CPU called the MULTIS, which is capable of handling the dynamically created data of multiple tasks in on-chip storage. This ability enables tasking systems to benefit from the use of large on-chip memories such as those found in RISC (reduced-instruction-set computer) technologies. Other features of the architecture include efficient interrupt handling and provision for register-based task local, procedure-global dynamic storage. >

Register window management for a real-time multitasking RISC

Selective register save and restore upon context switch using trap

One characteristic of RISC architectures is the availability of a large register bank, usually used as a LIFO stack to house the activation records of procedures. In a multitasking situation, RISC designers have suggested that this stack be copied at every task-context switch. The overhead of this copying is high, and it is frequently cited as the reason for which stack-based architectures should not be used in a multitasking situation. The architecture presented facilitates multitasking by allowing multiple register stacks, created dynamically, to be supported with the same overhead as sequential procedure calls. In addition, it allows registers to be used for other non-LIFO structures, such as object or class instantiations. These register-housed data structures can be accessed by any task or procedure unit. >

D.J. Quammen

Papers

Register window management for a real-time multitasking RISC

A RISC architecture for multitasking