This paper presents the design and the analysis of power efficient binary content addressable memory (PEBCAM) core cells using the energy recovery principle of adiabatic logic. Generally, in the design of adiabatic CAM, the storage array is built by using a basic CAM cell, but the peripheral circuits are realized by using different adiabatic logic structures. In this paper, we propose the design of 3 novel power efficient binary content addressable memory core cells (PEBCAM core cells) using adiabatic logic, namely improved efficient charge recovery logic (IECRL) CAM core cell, positive feedback adiabatic logic (PFAL) CAM core cell and pass transistor adiabatic logic (PAL) CAM core cell. Memory arrays of size 4 $$\times $$? 4 were designed and implemented using the proposed PEBCAM core cells in 45nm CMOS technology. It was found that recovery of dissipated power using adiabatic logic was better than the other CAM structures. The simulation results of the PEBCAM-IECRL CAM proved to be better with a power saving of 77.8% than the conventional adiabatic CAM structures. The circuits were designed using 45nm CMOS technology with a sinusoidal power clock of 1 V and other node voltages at 0.7 V using Cadence Virtuoso.

Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells

Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.

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Zi-CAM: A Power and Resource Efficient Binary Content-Addressable Memory on FPGAs

We propose a novel edit distance-tolerant content addressable memory (EDAM) for energy-efficient approximate search applications. Unlike state-of-the-art approximate search solutions that tolerate certain Hamming distance between the query pattern and the stored data, EDAM tolerates edit distance, which makes it especially efficient in applications such as text processing and genome analysis. EDAM was designed using a commercial 65 nm 1.2 V CMOS technology and evaluated through extensive Monte Carlo simulations, while considering different process corners. Simulation results show that EDAM can achieve robust approximate search operation with a wide range of edit distance threshold levels. EDAM is functionally evaluated as a pathogen DNA detection and classification accelerator. EDAM achieves up to 1.7× higher F1 score for high-quality DNA reads and up to 19.55× higher F1 score for DNA reads with 15% error rate, compared to state-of-the-art DNA classification tool Kraken2. Simulated at 667 MHz, EDAM provides 1, 214× average speedup over Kraken2. This makes EDAM suitable for hardware acceleration of genomic surveillance of outbreaks, such as the ongoing Covid-19 pandemic.

EDAM: edit distance tolerant approximate matching content addressable memory

This paper proposes a novel Hamming distance tolerant content-addressable memory (HD-CAM) for energy-efficient in-memory approximate matching applications. HD-CAM exploits NOR-type based static associative memory bitcells, where we add circuitry to enable approximate search with programmable tolerance. HD-CAM implements approximate search using matchline charge redistribution rather than its rise or fall time, frequently employed in state-of-the-art solutions. HD-CAM was designed in a 65 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm { \text {n} \text {m} }$ </tex-math></inline-formula> 1.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm { \text {V}}$ </tex-math></inline-formula> CMOS technology and evaluated through extensive Monte Carlo simulations. Our analysis shows that HD-CAM supports robust operation under significant process variations and changes in the design parameters, enabling a wide range of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mismatch threshold</i> (tolerable Hamming distance) levels and pattern lengths. HD-CAM was functionally evaluated for virus DNA classification, which makes HD-CAM suitable for hardware acceleration of genomic surveillance of viral outbreaks, such as Covid-19 pandemics. 

/pdf/hamming-distance-tolerant-content-addressable-memory-hd-cam-2l7me0hr.pdf

Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification

We propose a novel edit distance-tolerant content addressable memory (EDAM) for energy-efficient approximate search applications. Unlike state-of-the-art approximate search solutions that tolerate certain Hamming distance between the query pattern and the stored data, EDAM tolerates edit distance, which makes it especially efficient in applications such as text processing and genome analysis. EDAM was designed using a commercial 65 nm 1.2 V CMOS technology and evaluated through extensive Monte Carlo simulations, while considering different process corners. Simulation results show that EDAM can achieve robust approximate search operation with a wide range of edit distance threshold levels. EDAM is functionally evaluated as a pathogen DNA detection and classification accelerator. EDAM achieves up to 1.7× higher F1 score for high-quality DNA reads and up to 19.55× higher F1 score for DNA reads with 15% error rate, compared to state-of-the-art DNA classification tool Kraken2. Simulated at 667 MHz, EDAM provides 1, 214× average speedup over Kraken2. This makes EDAM suitable for hardware acceleration of genomic surveillance of outbreaks, such as the ongoing Covid-19 pandemic. 

Edam

This paper presents the design of a complete Energy Efficient Charge Recovery Adiabatic Logic Content Addressable Memory using the energy recycling principle of adiabatic logic. Generally, in the design of adiabatic CAM, the storage array is built by using a basic CAM cell but the decoders which drives the bit lines and word lines are realized by using different adiabatic logic structures such as Complementary Pass Transistor Adiabatic Logic (CPAL), Split-level Charge Recovery Logic (SCRL), Two Level Adiabatic Logic (2LAL), Quasi-Adiabatic Logic, Positive Feedback Adiabatic Logic (PFAL), Two Phase Adiabatic Static Clocked Logic (2PASCL), Pre-resolve and Sense Adiabatic Logic (PSAL), Efficient Charge Recovery Adiabatic Logic (ECRL), etc., In this paper, we propose an innovative complete ECRL CAM cell built with ECRL bit line drivers and word line drivers. Thus charges of node capacitances on these lines along with that in the cells are well recovered. An evaluation is made between the conventional CAM Architecture and the proposed ECRL CAM Architecture. The simulation results of a 4×4 adiabatic logic Complete ECRL CAM proves to be better with a power saving of 65% than the conventional CAM. The circuits are designed using 180nm CMOS technology with a power supply of 1.8V using Cadence Virtuoso.

D. Jothi

Papers

Design and Analysis of Power Efficient Binary Content Addressable Memory (PEBCAM) Core Cells

A completely efficient charge recovery adiabatic logic content addressable memory