The IBM logic-based eDRAM (embedded DRAM) technology integrates a trench DRAM (dynamic random access memory) storage-cell technology into a logic-circuit technology, merging the two previously separate technologies. Since its introduction in the 1970s, the DRAM technology has been driven by cost while the logic technology has been driven by speed, leading to an ever-widening gap between slower memory and faster logic devices. That has led to the need for increasingly complex levels of memory hierarchies, resulting in considerable degradation of system performance despite many design and architecture compromises. DRAM can provide six to eight times as much memory as SRAM (static random access memory) in the same area, but has been too slow to be used at any cache level. Our studies, highlighted in this paper, indicated that the use of logic-based DRAM could resolve that difficulty--and was necessary for integrating systems on a chip. This has led to the inclusion of logic-based eDRAM as a memory option in the IBM ASICs (application-specific integrated circuits) product.

Logic-based eDRAM: origins and rationale for use

A highly concurrent superscalar second-generation family of RISC workstations and servers is described. The RISC System/6000 family is based on the new IBM POWER (performance optimization with enhanced RISC) architecture; the hardware implementation takes advantage of this powerful RISC architecture and employs sophisticated design techniques to achieve a short cycle time and a low cycles-per-instruction (CPI) ratio. The RS/6000 CPU features multiple-instruction dispatch, multiple functional units that operate concurrently, separate instruction and data caches, and zero-cycle branches. In this superscalar implementation, at a given cycle the equivalent of five operations can be executed simultaneously ( a branch, a condition-register operation, and a floating-point multiply-add).

The IBM RISC System/6000 processor: hardware overview

Branch instructions form a significant fraction of executed instructions, and their design is thus a crucial component of any architecture. This paper examines three alternatives in the design of branch instructions: delayed vs. non-delayed branches, one- vs. two-instruction branches, and the use or non-use of condition codes. Simulation and analytical techniques are used to provide quantitative comparisons between these choices.

An evaluation of branch architectures

Advances in technology have provided a continuing improvement in processor speed and capacity of attached main memory. The increasing gap between main memory and processor cycle times has required increasingly more levels of caching to prevent performance degradation. The net result is that the inherent delay of a memory hierarchy associated with any computing system is becoming the major performance-determining factor and has inspired many types of analysis methods. While an accurate performance-evaluation tool requires the use of trace-driven simulators, good approximations and significant insight can be obtained by the use of analytical models to evaluate finite cache penalties based on miss rates (or miss ratios) and queuing theory combined with empirical relations between various levels of a memory hierarchy. Such tools make it possible to readily determine trends in performance vs. changes in input parameters. This paper describes such an analysis approach--one which has been implemented in a spreadsheet and used successfully to perform early engineering tradeoffs for many uniprocessor and multiprocessor memory hierarchies.

Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory

A cache memory having rows of memory cells, each row having at least first and second blocks of memory cells. Each memory cell stores a data signal, has at least one word line input, and at least one bit line input/output. A word line connects the word line inputs of at least first, second, third, and fourth memory cells in a row of the cache memory. The first and third memory cells are contained in the first block, while the second and fourth memory cells are contained in the second block. First and second sense amplifiers or write drivers are provided for reading data from or writing data to memory cells. First and second switches having control inputs connect the bit line inputs/outputs of the first and second memory cells, respectively, to the first sense amplifier/write driver. Third and fourth switches having control inputs switchably connect the bit line inputs/outputs of the third and fourth memory cells, respectively, to the second sense amplifier/write driver. The control inputs of the first, second, third, and fourth switches are capable of being independently actuated. Selection means, such as an address decoder, independently actuate either the first and third switches to connect memory cells only in the first block to the sense amplifiers, or the first and fourth switches to connect memory cells in both the first and second blocks to the sense amplifiers.

Bit line switch array for electronic computer memory

This paper examines how architecture, the definition of the instruction set and other facilities that are available to the user, can influence the implementation of a very large scale integration (VLSI) microsystem. The instruction set affects the system implementation in a number of direct ways. The instruction formats determine the complexity of instruction decoding. The addressing modes available determine not only the hardware needed (multiported register files or three-operand adders), but also the complexity of the overall machine pipeline as greater variability is introduced in the time it takes to obtain an operand. Naturally, the actual operations specified by the instructions determine the hardware needed by the execution unit. In a less direct way, the architecture also determines the memory bandwidth required. A few key parameters are introduced that characterize the architecture and can be simply obtained from a typical workload. These parameters are used to analyze the memory bandwidth required and indicate whether the system is CPU- or memory-limited at a given design point. The implications of caches and virtual memories are also briefly considered.

D. T. Ling

Papers

Architecture implications in the design of microprocessors