An ultra high-speed latched comparator using a controlled amount of positive feedback cell has been designed in TSMC 0.18 μm CMOS technique. Transmission gate (TG) switches are used to implement the preamplifier circuit. The use of TG switches results in a reduction in the power consumption of the high-speed comparator as well as clock feedthrough and the effect of charge injection. The simulation results demonstrate that it can work at 1.25 GHz suitable for high speed applications, and consumes 273.6 μW with a power supply of 1.8 V at 100 MHz and Monte Carlo simulation shows that the comparator has a low offset voltage approximately 0.499 mV.

A high-speed latched comparator with low offset voltage and low dissipation

Modern communication and signal processing is dependent on the high speed and low power consumption of the Analog-to-Digital converters (ADC) to a very large extent. Comparator is the basic building block of the ADCs which compares the two set of variables and change the input analog signal in digital. In this paper a new design of double tail comparator is proposed for high frequency of data conversion and is compared with the best available recently proposed double tail comparator design in term of area on chip power utilization, delay consideration and PDP. For a frequency higher than 350 MHz the power consumption is less for the proposed double tail comparator design, which keeps on getting better with every rising frequency. The maximum frequency of operation is also increased from 1.7 GHz to 2.5 GHz along with lesser delay which is significant considering the need of high speed devices. Apart from the proposed DT comparator shows an improvement of 23.57% in terms of area than the previous best design.

New improved high speed low power double tail comparator design for 2.5 GHz input signal

Analog Comparator is designed to compare two analog inputs and outputs a logical signal indicating which of the inputs is greater or lesser. Comparators, being an essential building block of most high speed devices like Analogue to Digital Converters, are one of the most important components used in signal processing and communication systems. Also it plays a challenging role in high speed mixed signal system designs. In this paper, we have presented an ultra-high speed simple dynamic comparator design using 65nm UMC technology. The circuit is operating at a clock frequency of 6.66GHz and input signal frequency of around 3.33GHz. The propagation delay is minimized to about 47.14ps with a low noise of about 0.531fV2/Hz which makes the proposed structure favourable for Flash or Pipelined data conversion applications. However, it uses only a total of 12 MOS transistors with minimum W/L ratios to make the circuit simple and area efficient, without affecting its performance. With the enhancement of speed and keeping other parameters like power & energy at its optimum value, this comparator circuit is a novel design that can be used in any high speed applications.

Design of low noise high speed novel dynamic Analog Comparator in 65nm technology

In the proposed single-stage comparator, the comparison cycle is divided into six phases to cancel the static offset and then perform comparison. Operations, except in reset, are scheduled by applying small voltage variations, up to 200mVolts, on bulk terminals of concurrently used negative and positive feedback PMOS devices. Negative feedback restricts the gain of the main comparison and the offset cancellation loop during pre-amplification. Pre-amplification phase is intentionally added before the latch operation to remove the concerns of the erroneous latch of unpredictable residues which might be remained across the reset switch from the last comparison. The negative and positive feedback devices also impart in offset cancellation loop to provide high loop gain and remove the need for auxiliary amplifier. Worst-Case simulation results confirms that the proposed comparator can detect 1.5mVolts input difference, at all process corners, in presence of 15mVolts input offset voltage, at 800MS/s comparison rate. The Monte-Carlo analysis for 100 iterations on input offset voltages shows that input referred offset would be improved to 150µV while was 6mVolts at 1σ before correction. Power consumption is 0.78mW at 800MS/s comparison speed. Simulations are performed using the BSIM3 model of a 0.18µm CMOS technology.

A 800MS/s, 150µV input-referred offset single-stage latched comparator

A novel and reliable high-resolution and high-speed SAR ADC is presented in this paper. In the proposed article, a new compound R-2R/C structure is utilized in order to achieve both high-resolution and high-speed SAR ADC simultaneously. As simulation results verify that, at 1.8 V and 100 MS/s sampling rate with a Nyquist input, the ADC achieves an SNDR of 76.1 dB as well. The power consumption and FOM parameter of the proposed ADC are 5.18mW and 9.65fJ per conversion step respectively. Meanwhile, 300 times iterations in the transient Monte-Carlo analysis are applied, too. Also, the maximum Integral Nonlinearity (INL) and the maximum Differential Nonlinearity (DNL) are −0.45/+0.56LSB and −0.44/+0.37 LSB respectively. Simulation results of the proposed structure are simulated using the HSPICE BSIM3 model of a standard 0.18μm CMOS process.

A new 13-bit 100MS/s full differential successive approximation register analog to digital converter (SAR ADC) using a novel compound R-2R/C structure

A new high speed, low power and high resolution comparator architecture is presented. Offset voltage cancellation on latch stage and eliminating the preamplifier stages before regeneration latch in conventional architectures is the key idea proposed in this paper. Equivalent input referred offset voltage is dramatically reduced by controlled negative feedback loop and negative resistance of regeneration latch. The Monte-Carlo simulation results for the designed comparator in 0.18µm CMOS process show that equivalent input referred offset voltage is 0.2mV at 1 sigma while it was 26mV at 1 sigma before offset cancellation. The comparator operates in 500MHz clock frequency while dissipates 600µW from a 1.8V supply.

Dabbagh-Sadeghipour Khosrov

Papers

A new offset cancelled latch comparator for high-speed, low-power ADCs