This work describes an investigation into the performance of packaging materials, developed with a specific aim in improving thermal performance, such as silver-sintered materials that perform both die-attach and thermal-interface-material (TIM) duties. The test vehicles under study consist of a flip-chip BGA package (die size: 10.2×10.2×0.3mm in a package of 21×21×1.5mm) and a molded QFN package (thin die size: 5×5×0.070mm in a package of 8×8×0.7mm) Parametric thermal modeling using Finite-Volume-Method Simulation thermal modeling software covers the effect on package thermal resistance (junction-to-case) due to package geometry parameters, interface thickness (bond-line thickness), void coverage, thermal conductivity and contact resistance. In addition to steady-state thermal resistance, transient analysis of the QFN structure under a high frequency operational power profile is also investigated. Finally, experimental thermal characterization of the device for thermal resistance (junction-to-case) is also conducted under time-zero conditions and post-reliability tests (such as Moisture Sensitivity (JESD22-A113-D MSL3 and MSL1), Temperature Cycling (JESD22-A104-G TC-condition B or C), High Temperature Storage (HTS, +150°C and 1000 hours) and Unbiased Highly-Accelerated Stress Test (HAST)).

Modeling and characterization of the thermal performance of advanced packaging materials in the flip-chip BGA and QFN packages

In this work, the thermal analysis is performed to investigate and improve the heat dissipation capability of the fan-out eWLP POP structure. The simulation scheme was validated with the available experimental results conducted previously by Hoe et al. [9]. The 3-D package studied is shown in Figure 1. The thermal performance of the initial POP structure is evaluated as the baseline case. Then, the impact of the internal factors (thermal properties and geometries) on heat dissipation capability of the 3-D packages is investigated and compared. In the mobile device scenario, passive cooling solutions are explored for heat removal improvement. The topside thermal cap provides additional thermal paths between the top and bottom packages, and achieves pronounced temperature decrease. The package lid of larger size and direct thermal path to PCB has enhanced the heat spreading capability, and achieved effective heat conduction from both top and bottom packages to the outside environment. A total heating power of 4 W in the POP can be dissipated, while maintaining the maximum die temperature under the operation limit (85 °C).

Heat Dissipation Capability of a Package-on-Package Embedded Wafer-Level Package

In the embedded wafer-level packaging field, the embedded micro wafer level package (EMWLP) technology leverages on fan-out redistribution connections, keeping the reliance on wire-bonding and flip-chip bump connections to a minimum, thus streamlining the packaging process. As the embedded micro wafer level packaging (EMWLP) technology evolves to capitalize on package-on-package (POP) technology, this study's parametric thermal modeling focuses on analyzing the thermal impact of increased density in a low thermal conductivity packaging material. The package design in this work has the following specifications: the memory EMWLP (die size: 7×7×0.2mm) on logic EMWLP structure (die size : 8×8×0.2mm), sized 12×12×0.9mm in total. The POP structure, furthermore, incorporates through-mold-interconnects (TMI) in the bottom logic package to provide short electrical connection from the top package to the board level. The impact on multi-package thermal resistance is then studied as the following parameters vary: power dissipation (in both packages); mold conductivity; number of TMIs; number of solder ball connections; inclusion and size of an interpackage heatslug; inclusion and thermal conductivity of a top heatspreader. The thermal management of the dies are also studied based on the above measures and was found to accommodate under 4W of total POP power. Finally, simulation results for a general system-level thermal modeling of the EMWLP POP in a cellphone scenario are also conducted with passive thermal management solutions proposed.

Thermal modeling and simulation of a package-on-package embedded micro wafer level package (EMWLP) structure at the package and system-level

The thermal performance of 2.5D package with integrated processor and 2 memory stacks has been investigated, and 4 types of thermal lids without increasing the package footprint has been designed and evaluated. The heat dissipation capabilities of different structures were first analyzed under natural convection condition, and then forced air cooling condition was considered in portable device scenario. The effect of stiffener on the heat dissipation and thermal crosstalk has been analyzed. Under natural convection, providing heating power to both processor and memory, a total power around 3W can be dissipated. With forced air cooling in limited space, the initial package can dissipate around 6.5W heating power. By using the designed thermal lid, the dissipated heating power can be increased by almost one time. The results and conclusions obtained will aid the thermal design of 2.5D package.

Heat dissipation capability of package with integrated processor and 3D-stacked memory

As electronic products tend to higher density and higher power, thermal management plays a key role in electronic package design, especially in CPU, ASIC and System-in-Package (SiP). The root cause of many product failures can be traced back to heat management, so reducing chip working temperature and improving device thermal performance are necessary requirements. We report on the design and implementation of a novel cooling structure for electronic packages, called the 'bottom heat spreader'. The bottom heat spreader has two main features. The first is that heat is removed from the side of the chip where heat is generated by transistor switching without relying solely on thermal conduction through the thickness of the die. To this end, an additional heat spreader is placed at the bottom of the die. The other feature is that the stiffener ring that provides a heat conduction path to the heat sink is a good thermal conductor. This structure provides another path of thermal conduction path to improve die cooling. Simulation reuslts indicate that the overall thermal resistance with the bottom heat spreader in place is 13.24% lower than the same sturcture without the bottom heat spreader. The bottom heat spreader is compatible with other cooling structure for added cooling performance.

A novel cooling structure for electronic package

In this paper, package-level thermal modeling of the embedded micro-wafer-level-packaging (EMWLP) package has been performed to extract the parametric trends for thermal design guidelines of an eccentric single active die embedded alongside an integrated passive device (IPD), as shown in Fig.1 (with optional heat sink as a cooling solution). Exploratory thermal resistance modeling of an embedded two-die-stack has also been conducted. The effect of the mold compound used in the thermal models is further considered under the following parameters: mold thickness and thermal conductivity (0.4 W/mK to 2.5 W/mK). The effects of heat spreaders and heat sinks on the package thermal resistance are also studied, with due consideration paid to the above mold parameters. Furthermore, experimental characterization has been conducted to validate the package-level simulation for the single active die model, conforming to the JEDEC JESD 51-2A Thermal Measurements in Natural Convection standard. Finally, simulation results for a general system-level thermal modeling in both cellphone as well as laptop systems are also performed. Thermal management solutions for both scenarios, such as thermal vias and heat spreaders, are studied, with an optimal cooling solution proposed.

Damaragunath Pinjala

Papers

Thermal modeling and characterization of the embedded micro wafer level package (EMWLP) at the package- and system-level