An innovative post-silicon design validation methodology using recognized industry wide IREM imaging techniques in conjunction with full PC platform enablement was developed, and successfully applied to the IA-32 multiple-core (MC) Nehalem® microprocessor family [1]. Conventional structural based “tester” IREM characterization and debug techniques can, for the first time, be extended to the “platform” environment. IREM images can now be examined for design validations by running Windows/Linux® operating systems (OS) with market available benchmark software applications. This approach has been proven to be a faster, and significantly more cost effective, approach for post silicon design validation, power debug on low power Energy Star® states, and realistic customer applications.

Design validation on multiple-core CPU supported low power states using platform based infrared emission microscopy (PIREM) technique

In an embodiment, a processor includes a schedule logic to schedule a set of instructions for execution in an execution logic of the processor and a power analysis logic having a first calculation logic to calculate a maximum dynamic capacitance for at least a portion of the processor and a second calculation logic to calculate a dynamic capacitance estimate for execution of the set of instructions. A rescheduling of the set of instructions may occur based on a comparison of the dynamic capacitance estimate and the maximum dynamic capacitance. Other embodiments are described and claimed.

Managing dynamic capacitance using code scheduling

This article describes a comprehensive approach for silicon debug of a server chipset that includes a high-performance, third-generation chip-multithreaded (CMT) Sparc microprocessor. Efficiently debugging the chipset required a combination of debug features in silicon and system platforms, firmware support for debug, test generation tools, and debug data interpretation tools. Several useful lessons were learned in the process.

Comprehensive Approach to High-Performance Server Chipset Debug

This paper explains the characterization process for a DAC (Digital to Analog Converter). Parameters like DNL, INL, gain error, offset error, and their characterization processes have been discussed in detail. A remarkable change has struck the semiconductor industry where open-source Electronic Design Automation tools are being advertised to encourage people towards chip design. Tools like Open Lane support RTL to GDS flow. Companies like Google are facilitating free tape-outs of designs built using opensource PDKs like Sky Water 130 nm PDK. When the ICs are manufactured in large numbers, the fabrication process is not uniform hence, it causes variations in device behavior. Process variations may result in faulty semiconductors that can only be detected when they are tested after the tape out is done. In this paper, characterization of a DAC IC (MCP4921) has been performed without the use of an industry level characterization board and industry-level chip programmer. Arduino Uno which is an open-source micro controller has been used to program the IC by establishing an SPI interface with the DAC IC and the parameters have been measured using instruments like oscilloscope and source measure units which have been automated using Python. Python is also used to store the set of data obtained from the IC and this data is later postprocessed to calculate DC parameters like DNL, INL and Gain Error.

Post Silicon Characterization of Digital to Analog Converter using Arduino Uno

As performance per Watt concept being adapted on CPU's performance, a comprehensive post-silicon design methodology on chip power characterization, debug, and validation developed for an energy-efficient product performance become ever more important. An infrared photon-emission (IREM) based technique has been established to meet the needs. With those developed tool capabilities, we can validate simulated fullchip power, determine the causes of excessive power leakage, generate die power and thermal maps, and eventually optimize follow-on designs for power performance. This newly developed techniques have been applied and proven reusable on multiple core microprocessors fabricated under 90 nm and 65 nm CMOS technology. Examples of 5-8% power saving as compared with the first silicon data are presented here to demonstrate the success on debug and design optimization on full chip power.

Daniel Lu

Papers

Post-Silicon Design Methodology on Chip Power Characterization, Validation, and Debug Applied on High Performance Per Watt Microprocessor